SY10H641JZ-TR Allicdata Electronics
Allicdata Part #:

SY10H641JZ-TR-ND

Manufacturer Part#:

SY10H641JZ-TR

Price: $ 0.00
Product Category:

Integrated Circuits (ICs)

Manufacturer: Microchip Technology
Short Description: IC CLK BUFFER 1:9 135MHZ 28PLCC
More Detail: Clock Fanout Buffer (Distribution) IC 1:9 135MHz 2...
DataSheet: SY10H641JZ-TR datasheetSY10H641JZ-TR Datasheet/PDF
Quantity: 1000
1 +: 0.00000
Stock 1000Can Ship Immediately
$ 0
Specifications
Series: Precision Edge®
Packaging: Tape & Reel (TR) 
Part Status: Discontinued at Digi-Key
Type: Fanout Buffer (Distribution)
Number of Circuits: 1
Ratio - Input:Output: 1:9
Differential - Input:Output: Yes/Yes
Input: PECL
Output: TTL
Frequency - Max: 135MHz
Voltage - Supply: 4.75 V ~ 5.25 V
Operating Temperature: 0°C ~ 85°C
Mounting Type: Surface Mount
Package / Case: 28-LCC (J-Lead)
Supplier Device Package: 28-PLCC (11.51x11.51)
Base Part Number: SY10H641
Description

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The SY10H641JZ-TR is a low power, high speed buffer optimal for clocking and timing applications. It has a wide supply voltage range of 1.2V to 3.6V and a low power consumption of just 10μ to 25μ A, making it ideal for applications requiring high accuracy and little power, such as for use in personal computers, servers, embedded systems, and networking/telecommunications, among others.

The SY10H641JZ-TR is a 3-state clock driver which is able to drive one, two, four and eight outputs in a single package. It offers a low output skew with jitter and has a low ground bounce to ensure the clock signal does not get corrupted. Furthermore, the device features an automatic power down mode for improved power efficiency. The buffer includes an asynchronous clear function to allow quick reset of all outputs in the event of a fault.

Regarding its operation, the SY10H641JZ-TR supports two differential clock inputs, CLK and CLK_B, and two internally described logic functions, CLK_B positive edge and CLK_B negative edge. The clock inputs are combined and ANDed using an Or-AND logic array to create clock outputs. This combined logic allows the device to select between the differential clock inputs or synchronized clocks. The outputs and the leakage current of the device can be adjusted with the control pin, CTL, when the clock inputs are in a high or low state.

The SY10H641JZ-TR has two modes of operation: active and standby. When in active mode, the device\'s clock outputs reflect the logic inputs of CLK and CLK_B. When in standby mode, all of the clock outputs will be off and the output leakage current of each output will be less than 0.25μA.

The SY10H641JZ-TR is an ideal choice for clock tree applications that require low power, low noise, high switching speed and low output skew, making it suitable for many fields, including personal computers, servers, embedded systems, and networking/telecommunication. It is provided in a small and low profile 8-pin TSSOP package, which makes it well-suited for space-constrained applications.

The specific data is subject to PDF, and the above content is for reference

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