SY89833LMI

Series:	Precision Edge®
Packaging:	Tube
Part Status:	Discontinued at Digi-Key
Type:	Fanout Buffer (Distribution), Translator
Number of Circuits:	1
Ratio - Input:Output:	1:4
Differential - Input:Output:	Yes/Yes
Input:	CML, LVDS, LVPECL
Output:	LVDS
Frequency - Max:	2GHz
Voltage - Supply:	3 V ~ 3.6 V
Operating Temperature:	-40°C ~ 85°C
Mounting Type:	Surface Mount
Package / Case:	16-VFQFN Exposed Pad, 16-MLF®
Supplier Device Package:	16-MLF® (3x3)
Base Part Number:	SY89833

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SY89833LMI Application Field and Working Principle Clock Buffers, DriversSY89833LMI is a clock buffer from SYNOPSYS, a world leader in providing high-speed, high-performance clock solutions for data transmission and communications. The SY89833LMI delivers low-skew, high-performance clock outputs in a single device, and is ideal for demanding timing requirements and cost-sensitive applications. The SY89833 buffers two reference clock inputs, while providing three controlled-skew outputs and three buffered outputs all at low-skew, high-impedance and low-power.The SY89833LMI can be used in a variety of applications, such as communications, data storage, video/audio streaming and networking. The SY89833LMI is available in an 8-pin and 10-pin, Space-saving QFN package with a lead pitch of 0.5 mm, making it ideal for space-constrained applications. The SY89833LMI has a low-skew of 400 ps (typical) between the clock inputs and the outputs, and a low-power consumption of only 19 mW (typical). Additionally, the SY89833LMI has an integrated phase-locked loop (PLL) which enables the clock to be phase and frequency locked together.In terms of its working principle, the SY89833LMI features two identical clock dividers / buffers. Each of these dividers has two inputs and three outputs, one of which is a programmable, low-skew output. The two clocks are then synchronized together, which ensures the two independent clock inputs are phase and frequency locked. The SY89833LMI also employs a feed-forward PLL to making the frequency and phase lock.Once the two clock inputs are synchronized, the divider output clocks can be used as independent and mutually-synchronized clocks. The integrated PLL also acts as a programmable skew adjuster, as it provides a new internal unit set that can be programmed over a range of 600 ps. This allows for an improved clock jitter and an improved dynamic range of the output pulse width.The SY89833LMI also features an input pin that when driven, the device is ready for a new PLL startup delay time, allowing it to adapt to the changing environment of the application and providing additional control over clock skew. The SY89833LMI is available in both positive and negative logic, making it suitable for various applications.Overall, the SY89833LMI is an excellent choice for applications that require a low-skew, high-performance clock output such as communications, data storage, video/audio streaming, and networking. It is available in an 8-pin and 10-pin, space-saving QFN package with a lead pitch of 0.5 mm. The SY89833LMI is an ideal solution for cost-sensitive applications needing high-speed, high-performance clock solutions. It provides a low-skew of 400 ps between the clock inputs and the outputs and low-power consumption of 19 mW (typical). Furthermore, the integrated PLL and programmable skew adjuster adds additional advantages to the SY89833LMI, making it a perfect choice for many applications.

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