TPS7A0525PDBVR

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1. Description

The TPS7A0525PDBVR is an ultra-small, low quiescent current low-dropout regulator (LDO) that can source 200 mA with excellent transient performance. This device has an output range of 0.8 V to 3.3 V with a typical 1% accuracy. The TPS7A0525PDBVR, with ultralow IQ (1 µA), consumes very-low quiescent current for extending battery life in battery-powered applications. The device can be operated from rechargeable Li-Ion batteries, Liprimary battery chemistries such as Li-SOCl2, LiMnO2, as well as two- or three-cell alkaline batteries. The TPS7A05 is available with an active pulldown circuit to quickly discharge the output when disabled. The TPS7A05 is fully specified for TJ = –40°C to +125°C operation, and is available in standard X2SON (DQN), SOT-23 (DBV and DBZ), and DSBGA (YKA) packages.

2. Features

    1. Ultralow IQ: 1 µA (typ), 3 µA (max)

        – IGND: 6 µA (typ) at 200 mA

    2. Excellent transient response

    3. Packages:

        – 1.0-mm × 1.0-mm X2SON (4)

        – 0.65-mm × 0.65-mm DSBGA (4)

        – SOT-23 (5)

        – SOT-23 (3)

    4. Input voltage range: 1.4 V to 5.5 V

    5. Output accuracy: 1% typical, 3% maximum

    6. Available in fixed-output voltage:

        – 0.8 V to 3.3 V

    7. Very low dropout:

        – 235 mV (max) at 200 mA (3.3 VOUT)

    8. Active output discharge

    9. Foldback current limit

  10. Stable with a 0.47-µF or larger capacitor

3. Applications

    1. Wearable electronics

    2. Ultrabooks, tablets, E-readers

    3. Always-on power supplies

    4. Set-top boxes

    5. Gaming controllers, remote controls, toys, drones

    6. Wireless handsets and smart phones

    7. Portable and battery-powered equipment

4. Pin configuration

5. Pin Description

6. Feature Description

    1. Excellent Transient Response

        The device includes several innovative circuits to ensure excellent transient response. Dynamic biasing increases the IQ for a short duration during transients to extend the closed-loop bandwidth and improve the device response time during transients. Adaptive biasing increases the IQ as the dc load current increases, extending the bandwidth of the control loop. The device response time across the output voltage range is constant because of the use of a buffered reference topology, which keeps the control loop in unity gain at any output voltage.

    2. Active Discharge

        Devices with this option have an internal pulldown MOSFET that connects a 120-Ω resistor to ground when the device is disabled to actively discharge the output voltage. The active discharge circuit is activated when the device is disabled, in undervoltage lockout (UVLO), or in thermal shutdown. Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can flow from the output to the input. This reverse current flow can cause damage to the device. Limit reverse current to no more than 5% of the device-rated current.

    3. Low IQ in Dropout

        In most LDOs the IQ significantly increases when the device is placed into dropout, which is especially true for low IQ LDOs with adaptive biasing. The TPS7A05 detects when operating in dropout and disables the adaptive biasing, minimizing the IQ increase.

    4. Undervoltage Lockout (UVLO)

        The undervoltage lockout (UVLO) circuit monitors the input voltage (VIN) to prevent the device from turning on before VIN rises above the lockout voltage. The UVLO circuit also disables the output of the device when VIN falls below the lockout voltage. If the device includes the optional active discharge, the output is connected to ground with a 120-Ω pulldown resistor when VIN is below the lockout voltage.

    5. Enable

        The enable pin for the device is active high. The output of the device is turned on when the enable pin voltage is greater than the EN pin logic high voltage, and the output of the device is turned off when the enable pin voltage is less than the EN pin logic low voltage. A voltage less than the EN pin logic low voltage on the enable pin disables all internal circuits. At the next turn-on, any voltage on the EN pin below the logic low voltage ensures a normal start-up waveform with start-up ramp rate control, provided there is enough time to discharge the output capacitance. If shutdown capability is not required, connect EN to IN. VEN must not exceed VIN.

    6. Internal Foldback Current Limit

        The internal foldback current-limit circuit is used to protect the LDO against high-load current faults or shorting events. The foldback mechanism lowers the current limit as the output voltage decreases, and limits power dissipation during short-circuit events while still allowing for the device to operate at its rated output current. A foldback example for this device is that when VOUT is 90% of VOUT(nom) the current limit is ICL(typical); however, if VOUT is forced to 0 V the current limit is ISC (typical). In many LDOs the foldback current limit can prevent start-up into a constant-current load or a negatively-biased output. The foldback mechanism for this device goes into a brick-wall current limit when VOUT > 500 mV (typ), thus limiting current to ICL(typical) and, when VOUT is 0 V, the current is limited to ISC (typ) to ensure normal start-up to various loads. When IOUT < 1 mA (typ), the foldback current limit is removed to reduce IQ. Therefore, when IOUT < 1 mA (typ), the current-limit loop takes longer to respond to a current-limit event. Because of the often high power dissipation under these conditions, thermal shutdown can be activated during current-limiting events. To ensure proper operation of the current limit, minimize the inductance of the input and load. Continuous operation at current limit is not recommended.