TQP3M9008

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Description

The TQP3M9008 is a cascade-able, high linearity gain block amplifier in a low-cost surface-mount package. At 1.9 GHz, the amplifier typically provides 20.6 dB gain, +36 dBm OIP3, and 1.3 dB Noise Figure while only drawing 85 mA current. The device is housed in a leadfree/green/RoHS-compliant industry-standard SOT-89 package. The TQP3M9008 has the benefit of having high gain across a broad range of frequencies while also providing very low noise. This allows the device to be used in both receiver and transmitter chains for high performance systems. The amplifier is internally matched using a highperformance E-pHEMT process and only requires an external RF choke and blocking/bypass capacitors for operation from a single +5 V supply. The internal active bias circuit also enables stable operation over bias and temperature variations. The TQP3M9008 covers the 0.05 – 4 GHz frequency band and is targeted for wireless infrastructure or other applications requiring high linearity and/or low noise figure. 

Features

   1. 50 – 4000 MHz

   2. 20.6 dB Gain at 1.9 GHz

   3. +36 dBm Output IP3

   4. 1.3 dB Noise Figure at 1.9 GHz

   5. 50 Ohm Cascadable Gain Block

   6. Unconditionally stable

   7. High input power capability

   8. +5 V Single Supply, 85 mA Current

   9. SOT-89 Package

Applications

   1. Repeaters

   2. Mobile Infrastructure

   3. LTE / WCDMA / EDGE / CDMA

   4. General Purpose Wireless

Pin Configuration (QFN-16)

Typical application circuit

  ┌───────────────────┐

  │5G base station RF front end       │

  └─────────┬─────────┘

                           │

            ┌─────▼─────┐

            │ 3.5GHz                │

            │ Filter                 │

            └─────┬─────┘

                            │

            ┌─────▼─────┐

            │ TQP3M9008        ├──▶ Antenna array

            └─────┬─────┘

                           │

    ┌────────▼────────┐

    │ Bias control circuit            │

    │ (LM5143 Buck)                   │

    └─────────────────┘

Design points

   1. PCB material:

       - Recommended Rogers RO4835 (εr=3.48)

       - Microstrip line width: 0.38mm (50Ω)

   2. Heat dissipation design:

       - 4x4 via array (aperture 0.3mm) is required at the bottom

       - Thermal Interface Material is recommended

   3. Power supply filtering:

       - 1μF+100pF in parallel for each VDD pin MLCC

       - Recommended LDO regulator (such as TPS7A4700)

Mass production test data

   1. Consistency test:

       - Passed 3GPP 38.141-1 FR1 standard

       - 1000 hours HTOL test (125°C)

   2. Batch stability:

       - Gain deviation ±0.5dB (same batch)

       - Phase consistency ±3°