V105ADAG8

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1. Description

The V105ADAG8 LVDS display interface transmitter is designed to support pixel data transmission between a video processing engine and a digital video display. The dual channel LVDS output supports pixel rates up to 150 MHz, enabling compatibility with 1080p and WUXGA display resolutions. Total 67-bit LVCMOS/LVTTL input is provided. The V105A converts the 67 bit parallel input data into two 5-pair LVDS (Low Voltage Differential Signaling) serial data outputs, in odd/even pixel format. Input data can be clocked on the rising or falling edge of the input clock (selectable). In video applications the 35 data bits are normally divided into 10 bits for each R, G and B channel and 5 control bits (which includes VSYNC, HSYNC and DE).

2. Features

    1. Dual 32+3-bit LVTTL input supports up to 150 MHz pixel rate.

    2. Dual pixel, LVDS output supports 150 MHz pixel rate (compatible with 1080p and WUXGA resolution)

    3. Internal PLL requires no external loop filter

    4. Selectable rising or falling clock edge for data alignment

    5. Compatible with Spread Spectrum clock source

    6. Reduced LVDS output voltage swing mode (selectable) to minimize EMI

    7. Single 3.3 V supply

    8. Low power consumption CMOS design

    9. Power down mode

  10. Available in 144 pin LQFP package (14x14mm body size)

3. Pin configuration

4. Pin Descriptions