W25Q128JVSIM

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1. Describe

W25Q128JVSIM (128Mbit) serial flash memory provides storage solution space, pins and power for systems with limited capacity. The 25Q series provide devices with flexibility and performance far beyond ordinary serial flash memory. They are ideal for mapping code to RAM and executing code directly from dual/quad SPI (XIP) and storing voice, text, and data. The device uses a 2.7V to 3.6V single power supply, and the power consumption is as low as 1μA when the current is off. All equipment uses space-saving packaging. The W25Q128JV array is organized into 65,536 programmable pages, each page has 256 bytes. Up to 256 bytes can be programmed once. A group of 16 pages (4KB sector erase) and a group of 128 pages (32KB block erase), 256 groups (64KB block erase) or the entire chip (chip erase) can be erased. W25Q128JV has 4,096 erasable sectors and 256 erasable blocks respectively. The small 4KB sector allows the flexibility of applications that require data and parameter storage in larger sectors. W25Q128JV supports standard serial peripheral interface (SPI), dual/quad I/O SPI Quad Peripheral interface (QPI) and dual transfer rate (DTR): serial clock, chip select, serial data I/O0 (DI), I/O1 (DO), I/O2 (/WP) and I/O3 (/HOLD). Supports SPI clock frequency up to 133MHz, allowing dual I/O equivalent clock frequency of 266MHz (133MHz x 2), quad channel equivalent clock frequency of 532MHz (133MHz x 4), using fast read dual/quad I/O and QPI instructions Time I/O. These three transfer rates can outperform standard asynchronous 8-bit and 16-bit parallel flash memories. The continuous read mode allows efficient memory access to read 24-bit addresses with only 8 clock cycles of instruction overhead, allowing true XIP (execution in place) operations. 1 hold pin, write protection pin and programmable write protection, with top or bottom array control, providing further control flexibility. In addition, the device supports JEDEC standard manufacturer and device ID, a 64-bit unique serial number and three 256-byte security registers.

2. FEATURES

    1. New Family of SpiFlash Memories

        – W25Q128JV: 128M-bit / 16M-byte

        – Standard SPI: CLK, /CS, DI, DO, /WP, /Hold

        – Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold

        – Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3

        – QPI: CLK, /CS, IO0, IO1, IO2, IO3

        – SPI/QPI DTR(Double Transfer Rate) Read

        – Software & Hardware Reset(1)

    2. Highest Performance Serial Flash

        – 133MHz Single, Dual/Quad SPI clocks

        – 266/532MHz equivalent Dual/Quad SPI

        – 66MB/S continuous data transfer rate

        – Min. 100K Program-Erase cycles per sector

        – More than 20-year data retention

    3. Efficient “Continuous Read” and QPI Mode

        – Continuous Read with 8/16/32/64-Byte Wrap

        – As few as 8 clocks to address memory

        – Quad Peripheral Interface (QPI) reduces instruction overhead

        – Allows true XIP (execute in place) operation

    4. Low Power, Wide Temperature Range

        – Single 2.7 to 3.6V supply

        – <1µA Power-down (typ.)

        – -40°C to +85°C operating range

        – -40°C to +105°C operating range

    5. Flexible Architecture with 4KB sectors

        – Uniform Sector/Block Erase (4K/32K/64K-Byte)

        – Program 1 to 256 byte per programmable page

        – Erase/Program Suspend & Resume

    6. Advanced Security Features

        – Software and Hardware Write-Protect

        – Power Supply Lock-Down and OTP protection

        – Top/Bottom, Complement array protection

        – Individual Block/Sector array protection

        – 64-Bit Unique ID for each device

        – Discoverable Parameters (SFDP) Register

        – 3X256-Bytes Security Registers with OTP locks

        – Volatile & Non-volatile Status Register Bits

    7. Space Efficient Packaging

        – 8-pin SOIC 208-mil

        – 8-pad WSON 6x5-mm / 8x6-mm

        – 16-pin SOIC 300-mil (additional /RESET pin)

        – 24-ball TFBGA 8x6-mm (6x4/5x5 ball array)

        – Contact Winbond for KGD and other options

3. Pin Configuration

4. Pin Description

5. Packing specification