XC6123A632MR-G

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PMIC (Power Management Integrated Circuit) is a type of integrated circuit developed specifically for applications that require the improved energy efficiency and low power consumption provided by better power management. PMIC\'s particularly excel in controlling and optimizing systems with multiple power sources, and in applications where the power source needs to operate near its maximum efficiency. XC6123A632MR-G is a PMIC - Supervisors.

Application Field of XC6123A632MR-G

The XC6123A632MR-G is a precision voltage supervisor that provides a reset output whenever the supply voltage drops below a preset threshold. It is available in multiple packages such as Pin-6, SOT-89, WLCSP and its features are ultra-low power consumption, precision voltage detection, selectable reset active level and power good signal, adjustable reset delay time and adjustable output delay time.

XC6123A632MR-G is suitable for DeskTop, PortableComputers, Mobile Phones, Portable Devices,Tablet PCs, DSC, DVC, Smart Detectors and other low voltage, power sensitive systems. It is designed to monitor the core voltage of a system and, if the core voltage drops below a preset threshold, pull a reset signal low. This ensures that a system remains in a known operational state even during a voltage glitch or under voltage event. The adjustable reset delay time can be configured to minimize the effect of noise glitcheson the reset signal.

Working Principle of XC6123A632MR-G

The XC6123A632MR-G is a low-power voltage supervisor. It monitors an input voltage in the vicinity of +1.6V (+2.5V absolute maximum) with an accuracy of 200mV. An active-low reset signal is generated when the monitored voltage drops below the factory-set threshold VTH. The fixed VTH of XC6123A632MR-G is 1.47 V. If the reset signal is issued, the reset delay time (t RW ) will expire and enable the reset signal. This delay time, t RW , is factory set to 1.5 ms and is defined by the following equation,

t RW = [0.9V - VTH] x 2ms/V

Once the reset signal is issued, the reset output remains low until the input voltage rises above the hysteresis voltage V HY . The default hysteresis voltage of XC6123A632MR-G is typically 0.1 V. The reset output delay time, t RD , is factory set to 150ns and is defined by the following equation:

t RD = V HY x 150ns/V

Additionally, the XC6123A632MR-G has a built-in power-good (PG) signal. The PG signal is generated once the monitored voltage is higher than the VPG level (1.39V typical), and de-assertedwhen the monitored voltage drops below the VPG level. The PG delay time, t PDC , is factory set to 200µs, and is defined by the following equation:

t PDC = [VPG - Vth] x 200µs/V

The XC6123A632MR-G is a highly efficient voltage supervisor with a wide input voltage range, low-power consumption, adjustable reset delay time and adjustable reset output delay time. It is designed for applications that require the improved energy efficiency and low power consumption provided by better power management such as DeskTop, PortableComputers, Mobile Phones, Portable Devices,Tablet PCs, DSC, DVC, Smart Detectors and other low voltage, power sensitive systems.

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