XC2C32A-6QFG32I Allicdata Electronics
Allicdata Part #:

122-1973-ND

Manufacturer Part#:

XC2C32A-6QFG32I

Price: $ 0.00
Product Category:

Integrated Circuits (ICs)

Manufacturer: Xilinx Inc.
Short Description: IC CPLD 32MC 5.5NS 32QFN
More Detail: N/A
DataSheet: XC2C32A-6QFG32I datasheetXC2C32A-6QFG32I Datasheet/PDF
Quantity: 107
Stock 107Can Ship Immediately
Specifications
Series: CoolRunner II
Packaging: Tray 
Part Status: Active
Programmable Type: In System Programmable
Delay Time tpd(1) Max: 5.5ns
Voltage Supply - Internal: 1.7 V ~ 1.9 V
Number of Logic Elements/Blocks: 2
Number of Macrocells: 32
Number of Gates: 750
Number of I/O: 21
Operating Temperature: -40°C ~ 85°C (TA)
Mounting Type: Surface Mount
Package / Case: 32-VFQFN Exposed Pad
Supplier Device Package: 32-QFN (5x5)
Base Part Number: XC2C32A
Description

Due to market price fluctuations,if you need to purchase or consult the price.You can contact us or emial to us:   sales@allicdata.com


1. Describe

Xilinx CoolRunner™-II CPLD provides high-speed and The ease of use associated with the XC9500/XL/XV CPLD series and the extremely low-power versatility of XPLA3 Family in a single CPLD. It means exactly the same Part can be used for high-speed data communication/ Computing systems and leading portable products, Has the additional benefit of in-system programming. low Power consumption and high-speed operation are combined into an easy-to-use and cost-effective series. Clock technology and other energy-saving features Extend the user's power budget. The design features are It is supported from Xilinx ISE® 4.1i WebPACK tool.

2. Feature

    1. Optimized for 1.8V system

        - The industry's fastest low-power CPLD

        - Density from 32 to 512 macro cells

    2. The best 0.18 micron CMOS CPLD in the industry

        - Optimize the architecture to achieve effective logic synthesis

        - Multi-voltage I/O operation-1.5V to 3.3V

    3. Advanced system functions

        - The fastest system programming

           1. 1.8V ISP adopts IEEE 1532 (JTAG) interface

        - Instant reconfiguration (OTF)

        - IEEE1149.1 JTAG boundary scan test

        - Optional Schmitt trigger input (per pin)

        - Multiple I/O banks on all devices

        - Unparalleled low power management

           1. DataGATE external signal control

        - Flexible clock mode

          1. Optional DualEDGE trigger register

          2. Clock divider (÷ 2, 4, 6, 8, 10, 12, 14, 16)

          3. CoolCLOCK

        - Global signal option with macro unit control

           1. Multiple global clocks, each phase selection Macro cell

           2. Multiple global output enable

           3. Global Settings/Reset

        - Rich product terms clock, output enable and Set/reset

        - Efficient control item clock, output enable and Set/reset and share for each macro unit function block

        - Advanced design safety

        - Open drain output option for wired OR and LED drive

        - Optional bus hold, tri-state or weak pull-up selection Input/output pin

        - Optional configuration on unused I/O is grounded

        - Mixed I/O voltage compatible with 1.5V, 1.8V, 2.5V and 3.3V logic levels on all parts

        - SSTL2_1, SSTL3_1 and HSTL_1 on 128 Macro cells and denser devices

        - Hot swap

    4. PLA architecture

        - Excellent pin retention

        - 100% product term routable across functional blocks

    5. Broad package availability, including fine pitch:

        - Chip scale package (CSP) BGA, thin line BGA, TQFP, PQFP, VQFP and QFN packages

        - Lead-free suitable for all packages

    6. Use Xilinx and industry for design entry/verification Standard CAE tools

    7. Use Xilinx® to provide free software support for all densities WebPACK™ tool

    8. Industry-leading non-volatile 0.18 micron CMOS process

        - Guaranteed 1,000 program/erase cycles

        - Guaranteed 20 years of data retention

3. Function Block

The CoolRunner-II CPLD FBs contain 16 macrocells, with 40 entry sites for signals to arrive for logic creation and connection. The internal logic engine is a 56 product term PLA. All FBs, regardless of the number contained in the device, are identical. For a high-level view of the FB. At the high level, the product terms (p-terms) reside in a programmable logic array (PLA). This structure is extremely flexible, and very robust when compared to fixed or cascaded product term FBs. Classic CPLDs typically have a few product terms available for a high-speed path to a given macrocell. They rely on capturing unused p-terms from neighboring macrocells to expand their product term tally, when needed. The result of this architecture is a variable timing model and the possibility of stranding unusable logic within the FB. The PLA is different — and better. First, any product term can be attached to any OR gate inside the FB macrocell(s). Second, any logic function can have as many p-terms as needed attached to it within the FB, to an upper limit of 56. Third, product terms can be re-used at multiple macrocell OR functions so that within a FB, a particular logical product need only be created once, but can be re-used up to 16 times within the FB. Naturally, this plays well with the fitting software, which identifies product terms that can be shared. The software places as many of those functions as it can into FBs, so it happens for free. There is no need to force macrocell functions to be adjacent or any other restriction save residing in the same FB, which is handled by the software. Functions need not share a common clock, common set/reset, or common output enable to take full advantage of the PLA. Also, every product term arrives with the same time delay incurred. There are no cascade time adders for putting more product terms in the FB. When the FB product term budget is reached, there is a small interconnect timing penalty to route signals to another FB to continue creating logic. Xilinx design software handles all this automatically. 


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