10M08SAE144C8G Integrated Circuits (ICs)

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1. Feature

    1. Dual configuration flash memory for internal storage

    2. User Flash

    3. Immediate support

    4. Integrated analog-to-digital converter (ADC)

    5. Single-chip Nios II soft-core processor support

2. Embedded Multiplier

MAX 10 devices support up to 144 embedded multiplier blocks. Each block supports a single 18 × 18-bit multiplier or two separate 9 × 9-bit multipliers. By combining on-chip resources and external interfaces in Intel MAX 10 devices, you can build high-performance, low-system-cost, low-power DSP systems. energy consumption. You can use the Intel MAX 10 device alone or as a DSP device coprocessor to improve the price/performance ratio of a DSP system.

3. Embedded memory block

The embedded memory structure consists of columns of M9K memory blocks. Each M9K memory block of Intel MAX 10 devices provides 9 Kb of on-chip memory capable of running at frequencies up to 284 MHz. The embedded memory structure consists of columns of M9K memory blocks. Each M9K memory block in MAX 10 devices provides 9 Kb of on-chip memory. You can cascade memory blocks to form wider or deeper logical structures. You can configure M9K memory blocks as RAM, FIFO buffer, or ROM. Intel MAX 10 device memory blocks are optimized for applications such as high Throughput packet processing, embedded processor routines, and embedded data storage.

4. Clock and PLL

MAX 10 devices provide the following resources: a global clock (GCLK) network and a phase-locked loop (PLL) with a 116-MHz built-in oscillator. MAX 10 devices support up to 20 global clock (GCLK) networks operating at frequencies up to 450 MHz. The GCLK network has high drive strength and low skew. The PLL provides robust clock management and synthesis for device clock management, external system clock management, and I/O interface clocking.

5. High precision and low jitter PLLs have the following characteristics

    1. Reduce the number of oscillators required on the board

    2. Reduce device clock pins through multi-clock frequency synthesis Single reference clock source

    3. Frequency synthesis

    4. On-chip clock correction

    5. Jitter attenuation

    6. Dynamic Phase Shift

    7. Zero Delay Buffer

    8. Counter reconfiguration

    9. Bandwidth reconfiguration

  10. Programmable output duty cycle

  11. PLL cascade

  12. Reference clock switching

  13. ADC module driver

6. FPGA General Purpose I/O

MAX 10 I/O buffers support a range of programmable features. These features increase the flexibility of I/O usage and provide an alternative to reduce the use of external discrete components such as pull-up resistors and PCI clamping diodes.

7. External memory interface

Dual-supply Intel MAX 10 devices feature an external memory interface solution that uses the I/O elements and UniPHY IP on the right side of the device. Using this solution, you can create external memory interfaces to 16-bit SDRAM components with error correction coding (ECC).