10M25SAE144C8G Allicdata Electronics
Allicdata Part #:

544-3145-ND

Manufacturer Part#:

10M25SAE144C8G

Price: $ 0.00
Product Category:

Integrated Circuits (ICs)

Manufacturer: Intel FPGAs/Altera
Short Description: IC FPGA 101 I/O 144EQFP
More Detail: N/A
DataSheet: 10M25SAE144C8G datasheet10M25SAE144C8G Datasheet/PDF
Quantity: 1700
Lead Free Status / RoHS Status: Lead free / RoHS Compliant
Moisture Sensitivity Level (MSL): 3 (168 Hours)
Stock 1700Can Ship Immediately
Specifications
Series: MAX® 10
Part Status: Active
Lead Free Status / RoHS Status: --
Number of LABs/CLBs: 1563
Moisture Sensitivity Level (MSL): --
Number of Logic Elements/Cells: 25000
Total RAM Bits: 691200
Number of I/O: 101
Voltage - Supply: 2.85 V ~ 3.465 V
Mounting Type: Surface Mount
Number of Gates: --
Operating Temperature: 0°C ~ 85°C (TJ)
Package / Case: 144-LQFP Exposed Pad
Supplier Device Package: 144-EQFP (20x20)
Base Part Number: MAX 10 10M25
Description

Due to market price fluctuations,if you need to purchase or consult the price.You can contact us or emial to us:   sales@allicdata.com


1. Feature

    1. Dual configuration flash memory for internal storage

    2. User Flash

    3. Immediate support

    4. Integrated analog-to-digital converter (ADC)

    5. Single-chip Nios II soft-core processor support

2. Logic elements and logic array blocks

A LAB consists of 16 logic elements (LEs) and a LAB-wide control block. An LE is the smallest logical unit in the Intel MAX 10 device architecture. Each LE has four inputs, a four-input look-up table (LUT), a register, and output logic. A four-input LUT is a function generator that can implement any function with four variables.

3. Embedded multiplier and digital signal processing support

MAX 10 devices support up to 144 embedded multiplier blocks. Each block supports a single 18 × 18-bit multiplier or two separate 9 × 9-bit multipliers. By combining on-chip resources and external interfaces in Intel MAX 10 devices, you can build DSP systems with high performance, low system cost, and low power consumption. You can use the Intel MAX 10 device alone or as a DSP device coprocessor to improve the price/performance ratio of a DSP system.

4. Control the operation of the embedded multiplier block

    1. Parameterize related IP cores using the Intel Quartus Prime parameter editor

    2. Infer system design features provided by multipliers for MAX 10 devices directly using VHDL or Verilog HDL

    3. DSP IP cores

        - Common DSP processing functions such as Finite Impulse Response (FIR), fast Fourier Transform (FFT) and Numerically Controlled Oscillator (NCO) functions

        - Suite of common video and image processing functions

    4. Complete reference designs for end market applications

    5. DSP Builder for Intel FPGA Interface Tool between Intel Quartus Prime Software and MathWorks Simulink and MATLAB design environments

    6. DSP Development Kit

5. Embedded memory block

The embedded memory structure consists of columns of M9K memory blocks. Each M9K memory block of Intel MAX 10 devices provides 9 Kb of on-chip memory capable of running at frequencies up to 284 MHz. The embedded memory structure consists of columns of M9K memory blocks. Each M9K memory block in MAX 10 devices provides 9 Kb of on-chip memory. You can cascade memory blocks to form wider or deeper logical structures. You can configure M9K memory blocks as RAM, FIFO buffer, or ROM. MAX 10 device memory blocks are optimized for applications such as high-throughput packet processing, embedded processor programs, and embedded data storage.

6. Clock and PLL

MAX 10 devices provide the following resources: a global clock (GCLK) network and a phase-locked loop (PLL) with a 116-MHz built-in oscillator. MAX 10 devices support up to 20 global clock (GCLK) networks operating at frequencies up to 450 MHz. The GCLK network has high drive strength and low skew. The PLL provides robust clock management and synthesis for device clock management, external system clock management, and I/O interface clocking.

7. High precision and low jitter PLL features

    1. Reduce the number of oscillators required on the board

    2. Reduce device clock pins through multi-clock frequency synthesis from a single reference clock source

    3. Frequency synthesis

    4. On-chip clock correction

    5. Jitter attenuation

    6. Dynamic Phase Shift

    7. Zero Delay Buffer

    8. Counter reconfiguration

    9. Bandwidth reconfiguration

  10. Programmable output duty cycle

  11. PLL cascade

  12. Reference clock switching

  13. ADC module driver

8. FPGA General Purpose I/O

MAX 10 I/O buffers support a range of programmable features. These features increase the flexibility of I/O usage and provide an alternative to reduce the use of external discrete components such as pull-up resistors and PCI clamping diodes.

9. External memory interface

Dual-supply Intel MAX 10 devices feature an external memory interface solution that uses the I/O elements and UniPHY IP on the right side of the device. Using this solution, you can create external memory interfaces to 16-bit SDRAM components with error correction coding (ECC). The external memory interface feature is only available on dual-supply Intel MAX 10 devices.



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