23LC512T-I/SN

Series:	--
Packaging:	Tape & Reel (TR)
Part Status:	Active
Memory Type:	Volatile
Memory Format:	SRAM
Technology:	SRAM
Memory Size:	512Kb (64K x 8)
Clock Frequency:	20MHz
Write Cycle Time - Word, Page:	--
Memory Interface:	SPI - Quad I/O
Voltage - Supply:	2.5 V ~ 5.5 V
Operating Temperature:	-40°C ~ 85°C (TA)
Mounting Type:	Surface Mount
Package / Case:	8-SOIC (0.154", 3.90mm Width)
Supplier Device Package:	8-SOIC
Base Part Number:	23LC512

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Memory

The 23LC512T-I/SN is a high-density 4K x 8-bit low-power serial SRAM. It is intended for use in battery-powered applications, such as cellular phones, PDAs and digital still cameras, where it can provide both code execution and data storage. In addition, the 23LC512T-I/SN can be used in embedded systems replacing conventional parallel EEPROM or ROM memory. The 23LC512T-I/SN is a Static RAM (SRAM) which uses power for data retention when in standby mode. It is organized as 4K x 8 bits. This part is accessed in two address spaces through two separate pins, A0 and A1. Upon power-up, address space 0 (A0 high) is active. This memory device is oriented most often as an alternate version of the EEPROM or EPROM. The 23LC512T-I/SN operates from a single supply voltage ranging from 2.7V to 5.5V at clock frequencies up to 25 MHz. This part is programmable in the circuit through a single-wire micro-controller interface, I2C serial interface for control and data transfers. A halt (Sleep) mode is provided to reduce power consumption to two percent of active power. The 23LC512T-I/SN includes a 3-state non-multiplexing output driver to reduce power consumption. The device is available in a 8-pin SOIC package. The 23LC512T-I/SN can be easily integrated into any existing application that requires 4K bit data retention. It fits very easily into the existing 10 pin I2C footprint. This allows engineers to develop applications that use SRAM instead of EEPROM or ROM. The 23LC512T-I/SN device supports a powerful 2-wire serial interface for communication between digital systems. Every communication is preceded by a start condition and a 7-bit slave address which is used to identify the device on the bus. The clock source is generated from the master device and is used to clock data onto the data line. The device supports both the I2C address space and the standard 10 pin address space. The data on the data line is clocked by the master\'s clock and can either be in the write or read mode. In write mode, data is transferred from the master to the 23LC512T-I/SN and in read mode, data is transferred from the 23LC512T-I/SN to the master. Each data transfer is followed by an acknowledge bit to indicate that the data has been successfully transferred. The 23LC512T-I/SN device supports two operating modes, namely, the Active Mode and the Halt (Sleep) Mode. In the active mode, the device performs all operations including data writing, reading and chip-select operations. In the halt mode, the device acts as if it is powered down and it consumes only 2% of the active mode current. The 23LC512T-I/SN device also supports a Chip Enable (CE) which enables or disables the device, depending on the state of the CE pin. The CE pin is connected to the chip select (CS) of the device and is active “LOW” for active mode of the device.In summary, the 23LC512T-I/SN is a low-power Serial SRAM designed for applications in battery-powered devices such as cellular phones, PDAs and digital still cameras. It utilizes the three-state non-multiplexing output driver to reduce power consumption and supports an I2C serial Interface for control and data transfers. The device supports both the I2C address space and the standard 10 pin address space and can be easily integrated into existing applications. The device operates in two modes: Active Mode and Halt (Sleep) Mode, and is available in an 8-pin SOIC package.

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