5AGXMA5G6F35C6N

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1. DESCRIPTION

The Arria®V device family consists of the most comprehensive offerings of mid-range FPGAs ranging from the lowest power for 6 gigabits per second (Gbps) and 10 Gbps applications, to the highest midrange FPGA bandwidth 12.5 Gbps transceivers. The Arria V devices are ideal for power-sensitive wireless infrastructure equipment, 20G/40G bridging, switching, and packet processing applications, high-definition video processing and image manipulation, and intensive digital signal processing (DSP) applications.

2. Adaptive Logic Module

Arria V devices use a 28 nm ALM as the basic building block of the logic fabric. The ALM, as shown in following figure, uses an 8-input fracturable look-up table (LUT) with four dedicated registers to help improve timing closure in register-rich designs and achieve an even higher design packing capability than previous generations.

3. Variable-Precision DSP Block

    1. Configurable to support signal processing precisions ranging from 9 x 9, 18 x 18, 27 x 27, and 36 x 36 bits natively

    2. A 64-bit accumulator

    3. Double accumulator

    4. A hard preadder that is available in both 18- and 27-bit modes

    5. Cascaded output adders for efficient systolic finite impulse response (FIR) filters

    6. Dynamic coefficients

    7. 18-bit internal coefficient register banks

    8. Enhanced independent multiplier operation

    9. Efficient support for single-precision floating point arithmetic

  10. The inferability of all modes by the Intel Quartus Prime design software

4. Types of Embedded Memory

1. 20 Kb M20K or 10 Kb M10K blocks—blocks of dedicated memory resources. The M20K and M10K blocks are ideal for larger memory arrays while still providing a large number of independent ports.

2. 640 bit memory logic array blocks (MLABs)—enhanced memory blocks that are configured from dualpurpose logic array blocks (LABs). The MLABs are ideal for wide and shallow memory arrays. The MLABs are optimized for implementation of shift registers for digital signal processing (DSP) applica‐ tions, wide shallow FIFO buffers, and filter delay lines. Each MLAB is made up of ten adaptive logic modules (ALMs). In the Arria V devices, you can configure these ALMs as ten 32 x 2 blocks, giving you one 32 x 20 simple dual-port SRAM block per MLAB. You can also configure these ALMs, in Arria V GZ devices, as ten 64 x 1 blocks, giving you one 64 x 10 simple dual-port SRAM block per MLAB.

5. PLL Features

    1. Frequency synthesis

    2. On-chip clock deskew

    3. Jitter attenuation

    4. Counter reconfiguration

    5. Programmable output clock duty cycles

    6. PLL cascading

    7. Reference clock switchover

    8. Programmable bandwidth

    9. Dynamic phase shift

  10. Zero delay buffers

6. FPGA General Purpose I/O

    1. Programmable bus hold and weak pull-up

    2. LVDS output buffer with programmable differential output voltage (VOD ) and programmable preemphasis

    3. On-chip parallel termination (RT OCT) for all I/O banks with OCT calibration to limit the termination impedance variation

    4. On-chip dynamic termination that has the ability to swap between series and parallel termination, depending on whether there is read or write on a common bus for signal integrity

    5. Unused voltage reference ( VREF ) pins that can be configured as user I/Os ( Arria V GX, GT, SX, and ST only)

    6. Easy timing closure support using the hard read FIFO in the input register path, and delay-locked loop (DLL) delay chain with fine and coarse architecture