72811L10PFG

Bus Directional:	Bi-Directional
Base Part Number:	72811
Supplier Device Package:	64-TQFP (14x14)
Package / Case:	64-LQFP
Mounting Type:	Surface Mount
Operating Temperature:	0°C ~ 70°C
FWFT Support:	No
Retransmit Capability:	No
Programmable Flags Support:	Yes
Expansion Type:	Depth, Width
Series:	7200
Current - Supply (Max):	60mA
Voltage - Supply:	4.5V ~ 5.5V
Access Time:	6.5ns
Data Rate:	100MHz
Function:	Synchronous
Memory Size:	9K (512 x 9 x 2)
Part Status:	Active
Packaging:	Tray

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72811L10PFG – Logic – FIFOs Memory

FIFOs (First-In-First-Out memories) are all-digital memories which provide a method of organizing and controlling data flow, consisting of a time-independent succession of data words. They have the ability to temporarily store and transfer blocks of information to and from computers.The 72811L10PFG memory is a FIFO (First-In-First-Out) logic device. This device is ideal for buffering data between systems or operations. It is an 8-bit FIFO memory with dual-port capability, which can store up to 8 data words per memory location.An 8-bit FIFO is a dual-port memory device, where the data is stored on a single chip, so that the two ports can access the same data. The data is stored and retrieved from the same FIFO location in a first-in-first-out fashion.The 72811L10PFG memory features a low operating voltage, from 2.7V to 5.5V, making it suitable for many different types of systems, from battery powered communications devices to internal and external memories for sophisticated systems. It has a write access time of 1.35ns and a read access time of 1.55ns which allows the device to quickly move stored data in and out of memory.In terms of applications, the 72811L10PFG memory is used in several areas, such as backplane or databus applications, communication systems and data buffers. It can also be used as storage in Network Processors, ATM and other communication systems.In terms of the working principle, firstly, the 72811L10PFG receives/stores 8 data bits of information that are written in a first-in-first-out pipeline fashion. In other words, the data is written in one end of the FIFO, and can be read out from the other end.When writing data to the 72811L10PFG device, the write data port (WRDATA) can be loaded from an attached bus. The WREN control line activates a write strobe to accept the input data and store it in the FIFO at the address selected by the Memory Address pointer (MAP).For reading data from the 72811L10PFG device, the datapath from the chip to the bus is activated on asserting the RDEN control line. Data is retrieved at the address selected by the MAP, and loaded to the bus. The MAP is incremented afterwards, so that data can be sequentially read out.A key feature of the 72811L10PFG memory is the use of a Flow indicator (FLOW) line which is driven in active low. This pin is used to indicate whether the FIFO is full or empty. When the memory is full, the FLOW line will be asserted (low) to indicate that there is no more space to write data, and any data written after this will not be accepted. Similarly, when the 72811L10PFG is empty, the FLOW line will be asserted (low) to indicate that there is no more data stored in the FIFO.In addition, there are also several control lines which are available for increased user control. These include the Stop Enable (EN) and the Underflow (UFL) pins. The EN pin can be used to stop the FIFO’s operation, while the UFL pin is used to detect incorrect data flow or an underflow condition. It is also used to detect a reset condition, when the Memory Address pointer (MAP) is reset.In conclusion, the 72811L10PFG memory is a versatile logic-based device, featuring a first-in-first-out sequence structure, offering various functions and features for its application in many different systems and platforms. By utilizing a combination of the varying control lines and Flow indicator, it can easily control the data flow and transfer of data between applications.

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