74AC273PC

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1. Describe

74AC273PC and ACT273 have 8 edge triggers D-type flip-flop with independent D-type input and Q output. Common Buffered Clock (CP) and Master Clock Reset (MR) input load and reset (clear) all flip-flops at the same time. This register is fully edge-triggered. everyone's status Type D input, one setup time before LOW to HIGH The clock transitions are transferred to the Q output of the corresponding flip-flop. All outputs will be forced low independently of the clock or Data is entered via a low voltage level on the MR input. This device suitable for real output applications Only is required that the clock and master reset are Common to all storage elements.

2. Feature

    1. Ideal buffer for microprocessor or memory

    2. 8 edge-triggered D-type flip-flops

    3. Buffered common clock

    4. Buffered asynchronous master reset

    5. For clock-enabled versions, see 377

    6. Transparent latch version see 373

    7. 3-STATE version see 374

    8. Output source/sink 24mA

    9. 74ACT273 has TTL compatible inputs

3. Pin configuration

4. Pin Description