74HC138D

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1. Describe

The 74HC138D is a high speed CMOS 3 to 8 decoder fabricated with silicon gate C 2MOS technology. It achieves high-speed operation similar to equivalent LSTTL while maintaining the low power consumption of CMOS. When the device is enabled, 3 binary select inputs (A, B and C) determine which output (Y0-Y7) will go low. When the enable input G1 is held low or When G2A or G2B is held high, the decode function is disabled and all outputs go high. G1, G2A and address decoder with G2B input to simplify cascading and use as memory system. All inputs are equipped with protection circuits against electrostatic discharge or transient overvoltages.

2. Feature

    1. High speed: tpd = 16 ns (typ), VCC = 5 V

    2. Low power consumption: ICC = 4.0 µA (max), Ta = 25°C

    3. Balanced propagation delay: tPLH≈tPHL

    4. Wide operating voltage range: VCC(opr) = 2.0 to 6.0 V

3. Pin Description