74VHCT373ATTR

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Logic - Latches

74VHCT373ATTR is a type of logic latch belongs to SN74VHCT373 logic family introduced by Texas Instruments. This logic latch provides two latching outputs which are particularly suited to low power-consumption systems. This logic latch consists of two separate data latches which allow multicycle control of data flow. It operates over a wide supply voltage range of 2.3V to 5.75V and can be used in both commercial and industrial temperature ranges.

The 74VHCT373ATTR supports the following I/O interface-8-bit parallel input and 2- bit parallel output. The logic is edge- triggered and so the data is clocked at its input on the rising or falling edge. It consists of two separate 2:1 multiplexer, each of which is used to select one of two data sources for the latch. The selection between two data sources comes from the Common Latch Control(CLC) input.

The Common Latch Control (CLC) is a logical control input which, when brought to logic 0, enables the A side of the latch and holds it high. Conversely, when brought to logic 1, the B side of the latch is enabled and held low. The data outputs are symmetrical. This means when the input to the A side of the latch is in the HIGH position, both outputs will be in the LOW position, and when the input to the A side of the latch is in the LOW position, both outputs will be in the HIGH position.

Features

• Supply voltage: 2.3V to 5.75V
• Edge-triggered
• Input type: 2:1 multiplexer
• Symmetrical data outputs
• Low power consumption

Applications

The 74VHCT373ATTR logic latch has wide range of applications in low power-consumption systems. It is used in systems such as microcontrollers, digital signal processing systems, embedded systems, automotive systems, medical and industrial equipment and routing, switching and communications systems.

• Data buffering, latching and storage
• Memory applications
• Communication systems
• Automation and control systems
• Data acquisition and instrumentation

Working Principle

The 74VHCT373ATTR works on the principle of edge-triggered logic. It consists of two separate 2:1 multiplexer, each of which is used to select one of two data sources for the latch. The selection between two data sources comes from the Common Latch Control (CLC) input. When the CLC input is at logic 0, the A side of the latch is enabled and held high. On the other hand, when the CLC input is at logic 1, the B side of the latch is enabled and held low. Further, the data outputs are symmetrical which means that when the input to the A side of the latch is in the HIGH position, both outputs will be in the LOW position, and when the input to the A side of the latch is in the LOW position, both outputs will be in the HIGH position.

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