AD9251BCPZ-80

Due to market price fluctuations,if you need to purchase or consult the price.You can contact us or emial to us:   sales@allicdata.com

1. DESCRIPTION

The AD9251BCPZ-80 is a monolithic, dual-channel, 1.8 V supply, 14-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-andhold circuit and on-chip voltage reference. The product uses multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported and output data can be multiplexed onto a single output bus. The AD9251BCPZ-80 is available in a 64-lead RoHS Compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).

2. FEATURES

    1. 1.8 V analog supply operation

    2. 1.8 V to 3.3 V output supply

    3. SNR

        - 74.3 dBFS at 9.7 MHz input

        - 71.5 dBFS at 200 MHz input

    4. SFDR

        - 93 dBc at 9.7 MHz input

        - 80 dBc at 200 MHz input

    5. Low power

        - 33 mW per channel at 20 MSPS

        - 73 mW per channel at 80 MSPS

    6. Differential input with 700 MHz bandwidth

    7. On-chip voltage reference and sample-and-hold circuit

    8. 2 V p-p differential analog input

    9. DNL = ±0.45 LSB

  10. Serial port control options

        - Offset binary, gray code, or twos complement data format

        - Optional clock duty cycle stabilizer

        - Integer 1-to-8 input clock divider

        - Data output multiplex option

        - Built-in selectable digital test pattern generation

        - Energy-saving power-down modes

        - Data clock out with programmable clock and data alignment

3. APPLICATIONS

    1. Communications

    2. Diversity radio systems

    3. Multimode digital receivers

        - GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA

    4. I/Q demodulation systems

    5. Smart antenna systems

    6. Battery-powered instruments

    7. Hand held scope meters

    8. Portable medical imaging

    9. Ultrasound

  10. Radar/LIDAR

4. PRODUCT HIGHLIGHTS

    1. The AD9251 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.

    2. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use.

    3. A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/DATA timing and offset adjustments, and voltage reference modes.

    4. The AD9251 is packaged in a 64-lead RoHS compliant LFCSP that is pin compatible with the AD9268 16-bit ADC, the AD9258 14-bit ADC, the AD9231 12-bit ADC, and the AD9204 10-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.