ADS131M08IPBS

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1. Description

The ADS131M08IPBS is an eight-channel, simultaneouslysampling, 24-bit, delta-sigma (ΔΣ), analog-to-digital converter (ADC) that offers wide dynamic range, low power, and energy-measurement-specific features, making the device an excellent fit for energy metering, power metrology, and circuit breaker applications. The ADC inputs can be directly interfaced to a resistordivider network or a power transformer to measure voltage or to a current transformer or a Rogowski coil to measure current. The individual ADC channels can be independently configured depending on the sensor input. A lownoise, programmable gain amplifier (PGA) provides gains ranging from 1 to 128 to amplify low-level signals. Additionally, this device integrates channel-tochannel phase calibration and offset and gain calibration registers to help remove signal-chain errors. A low-drift, 1.2-V reference is integrated into the device reducing printed circuit board (PCB) area. Optional cyclic redundancy checks (CRCs) on the data input, data output, and register map maintain communication integrity. The complete analog front-end (AFE) is offered in a 32-pin TQFP package or a leadless 32-pin WQFN package and is specified over the industrial temperature range of –40°C to +125°C.

2. Features

    1. 8 simultaneously sampling differential inputs

    2. Programmable data rate up to 32 kSPS

    3. Programmable gain up to 128

    4. Noise performance:

        – 102-dB dynamic range at gain = 1, 4 kSPS

        – 80-dB dynamic range at gain = 64, 4 kSPS

    5. Total harmonic distortion: –100 dB

    6. High-impedance inputs for direct sensor connection:

        – Input impedance 330-kΩ for gains of 1, 2, and 4

        – Input impedance ≥ 1-MΩ for gains of 8, 16, 32, 64, and 128

    7. Programmable channel-to-channel phase delay calibration:

        – 244-ns resolution, 8.192-MHz fCLKIN

    8. Current-detect mode allows for extremely low power tamper detection

    9. Fast startup: first data within 0.5 ms of supply ramp

  10. Integrated negative charge pump allows input signals below ground

  11. Crosstalk between channels: –120 dB

  12. Low-drift internal voltage reference

  13. Cyclic redundancy check (CRC) on communications and register map

  14. 2.7-V to 3.6-V analog and digital supplies

  15. Low power consumption: 6.0 mW at 3-V AVDD and DVDD

  16. Packages: 32-pin TQFP or 32-pin WQFN

  17. Operating temperature range: –40°C to +125°C

3. Applications

    1. Electricity meters: commercial and residential

    2. Circuit breakers

    3. Protection relays

    4. Power quality meters

    5. Battery test equipment

    6. Battery management systems

4. Pin configuration

5. Pin Description

6. Clocking and Power Modes

The master clock can either be sourced externally to the CLKIN pin or generated internally using the onboard oscillator that requires a crystal connected between the XTAL1/CLKIN and XTAL2 pins. For optimal performance, the modulator sampling clock must be synchronous with the serial data clock (SCLK). The modulator sampling clock is derived from the master clock, which means the master clock must be synchronous with SCLK. Therefore, for best performance, supply a master clock to CLKIN and make sure data retrieval is synchronous to the clock signal at CLKIN. When not in use, turn the internal oscillator off to save power. The PWR[1:0] bits in the CLOCK register allow the device to be configured in one of three power modes: highresolution (HR) mode, low-power (LP) mode, and very low-power (VLP) mode. Changing the PWR[1:0] bits scales the internal bias currents to achieve the expected power levels. The external clock frequency must follow the guidance provided in the Recommended Operating Conditions table corresponding to the intended power mode in order for the device to perform according to the specification.

7. Code Example

This section contains example pseudocode for a simple program that configures and streams data from the ADS131M08. The pseudocode is written to resemble C code. The code uses several descriptive precompilerdefined constants that are indicated in upper case. The definitions are not included for brevity. The program works in three sections: MCU initialization, ADC configuration, and data streaming. This code is not optimized for using the fast startup feature of the ADS131M08. The MCU is initialized by enabling the necessary peripherals for this example. These peripherals include an SPI port, a GPIO configured as an input for the ADS131M08 DRDY output, a clock output to connect to the ADS131M08 CLKIN input, and a direct memory access (DMA) module that streams data from the SPI port into memory without significant processor intervention. The SPI port is configured to a 24-bit word size because the ADC default SPI word size is 24 bits. The CS pin is configured to remain low as long as the SPI port is busy so that it does not de-assert in the middle of a frame. The ADC is configured through register writes. A function referred to as adcRegisterWrite writes an ADC register using the SPI peripheral. No CRC data integrity is used in this example for simplicity, but is recommended. The ADC outputs are initially disablo short frames can be written during initialization consistent with the guidance provided in the Short SPI Frames section. The ADC is configured to output DRDY as pulses, the gain is changed to 32 for channels 1 and 3, and the DC block filter is used with a corner frequency of 622 mHz. Finally, the ADC word size is changed to 32 bits with an MSB sign extension to accommodate the MCU memory length and to allow for 32-bit DMA transfers. All other settings are left as defaults. Data streaming is performed by using an interrupt that is configured to trigger on a negative edge received on the GPIO connected to the DRDY pin. The interrupt service routine, referred to as DRDYinterrupt, sends six 32- bit dummy words to assert CS and to toggle SCLK for the length of the entire ADC output frame. The ADC output frame consists of one 32-bit status word, four 32-bit ADC conversion data words, and an optional 32-bit CRC word. The frame is long enough for output CRC even though the CRC word is disabled in this example. The DMA module is configured to trigger upon receiving data on the SPI input. The DMA automatically sends the ADC data to a predetermined memory location as soon as the data are shifted into the MCU through the SPI input.