ADM1810-5ARTZ-RL7 Integrated Circuits (ICs)

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Introduction

The ADM1810-5ARTZ-RL7 is a 3.2V fixed voltage supervisor with a built-in temperature compensation feature. It provides a solution to ensure system reset and/or power up sequences match hardware and software/firmware requirements along with superior immunity to contact bounce of reset signals. This device is capable of generating three independent assertion/deglitchable reset signals, each with their own dedicated reset window and two watchdog timers with selectable timeout periods.

This device belongs to PMIC - Supervisors category, which is designed to monitor the performance and conditions of a system. PMIC -Supervisors are mainly employed for power management, monitoring, resetting and status indication. PMIC supervisors generally include on-chip peripheral functions such as voltage monitoring, voltage and frequency regulation, and thermal management, among other features.

Application of ADM1810-5ARTZ-RL7

The ADM1810-5ARTZ-RL7 is particularly suitable for microprocessors and other memory devices. Its application includes industrial controllers and embedded applications which require system reset and/or power up sequencing. It can be used to detect undervoltage conditions, too, and also provide protection against accidental power down.

Such a device can be used in a wide range of applications – from automotive, to industrial control and home automation, to medical monitoring and instrumentation. Its immunity to contact bounce provides extra reliability and safety where signals may suffer from such problems.

Working Principle of ADM1810-5ARTZ-RL7

The ADM1810-5ARTZ-RL7 is a 3.2V fixed voltage supervisor that provides three independent assertion/deglitchable reset signals, each with their own dedicated reset window. When the input voltage falls below the reset voltage threshold (VRESET)set by a resistor divider, RESETn is asserted low. If a valid operating voltage is not maintained for the duration of the reset window (tRST), RESETn is re-asserted and the device is reset.

The device also includes two integrated watchdog timers with programmable time-out periods. The reset assertion and de-assertion duration (tRESET) is programmable by selecting a combination of the RESET_LEN_A, RESET_LEN_B, and RESET_LEN_C pins. The device contains a power-on delay circuit (tPOK)delay output RESET_B assertion until theVDD voltage reaches the preset trip point. Finally, theRESET_C signal has a Hardware Glitch Eliminator (HGE), which eliminates glitches with a duration of less than 4 ms.

Conclusion

The ADM1810-5ARTZ-RL7 provides a solution to ensure system reset and/or power up sequences match hardware and software/firmware requirements along with superior immunity to contact bounce of reset signals. Its applications include industrial controllers, embedded systems, medical monitoring, instrumentation and many more. Its unique features – three independent assertion/deglitchable reset signals, each with their own dedicated reset window and two watchdog timers with selectable timeout periods – make it a perfect choice in applications that require reliable and robust reset monitoring.

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