AT24C02D-SSHM-T Integrated Circuits (ICs)

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1. Describe

The Atmel® AT24C02D-SSHM-T provides 1,024/2,048 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized into 128/256 words of 8 bits each. The device's cascading capability allows up to eight devices to share a common 2-wire bus. These devices are optimized for many industrial and commercial applications that require low power consumption and low voltage operation. Both devices are available in space saving 8-lead SOIC, 8-lead TSSOP, 8-pad UDFN, 8-lead PDIP(1), 5-lead SOT23 and 8-bump VFBGA packages. The entire package family operates from 1.7V to 3.6V.

2. Feature

    1. Low voltage operation

        - 1.7V (VCC = 1.7V to 3.6V)

    2. Internal organization 128 x 8 (1K) or 256 x 8 (2K)

    3. I2C compatible (2-wire) serial interface

        - 100kHz Standard Mode, 1.7V to 3.6V

        - 400kHz Fast Mode, 1.7V to 3.6V

        - 1MHz Fast Mode Boost (FM+), 2.5V to 3.6V

    4. Schmitt trigger, filtered input for noise suppression

    5. Two-way data transmission protocol

    6. Write protect pin for full array hardware data protection

    7. Ultra-low operating current (1mA max) and standby current (0.8μA max)

    8. 8-byte page write mode

        - Allow partial page writes

    9. Random and sequential read modes

  10. Self-timed write cycle within 5ms

  11. High reliability

        - Endurance: 1,000,000 write cycles

        - Data retention: 100 years

  12. Green package option (Pb-Free/Halogen-Free/RoHS Compliant)

        - 8-Pin SOIC, 8-Pin TSSOP, 8-Pin UDFN, 8-Pin PDIP(1), 5-Pin SOT23, and 8-Ball VFBGA

  13. Mold sales options: Wafer Form and Tape and Reel

3. Pin configuration

4. Pin Description

5. Equipment operation and communication

The AT24C02D-SSHM-T operates as a slave device and utilizes a simple I2C compatible 2-wire digital serial interface to communicate with a host controller, commonly referred to as a bus master. The master initiates and controls all read and write operations to the slave devices on the serial bus, and both the master and the slave devices can send and receive data on the bus. The serial interface consists of only two signal lines: serial clock (SCL) and serial data (SDA). The SCL pin is used to receive the clock signal from the Master, while the bidirectional SDA pin is used to receive commands and data information from the master and send data back to the master. Data is always latched into the AT24C01D/02D on the rising edge of SCL and is always output from the device on the falling edge of SCL. Both the SCL and SDA pins contain integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. All command and data information is transmitted most significant bit (MSB) first. During the bus Communication, one data bit is transmitted per clock cycle, and after eight bits (one byte) of data have been transmitted, the receiving device must respond within the ninth cycle with an acknowledgment (ACK) or no acknowledgment (NACK) response bit Master The resulting clock cycles (ACK/NACK clock cycles); therefore, nine clock cycles are required for each byte of data transferred. There are no unused clock cycles during any read or write operations, so there must be no interruptions or interruptions in the data stream during each data byte transfer and ACK or NACK clock cycle. During data transfer, the data on the SDA pin can only change while SCL is low, and the data must remain stable while SCL is high. If the data on the SDA pin changes while SCL is high, a Start or Stop condition will occur. Start and Stop conditions are used to initiate and end all serial bus communication between master and slave devices. The number of data bytes transferred between start and stop conditions is unlimited, as determined by the master device. To idle the serial bus, both the SCL and SDA pins must be logic high state at the same time.