AT28C64E-12SU

Due to market price fluctuations, if you need to purchase or consult the price. You can contact us or emial to us:   sales@allicdata.com

AT28C64E-12SU is a member of the AT28C64E family of low voltage (1.8-3.6V) 8-Kbyte EEPROMs with an industry-standard; two-wire, I²C bus interface. The device provides 8192 bits of nonvolatile memory that are segmented into 1024 bytes (8 bits each). The memory is organized as 8 rows of 128 bytes, with each row sharing the same 8-bit data Bus. The principal feature of AT28C64E-12SU is a self-timed, self-terminated write operation, which requires a single control byte, input on the serial interface, followed by a variable number of data bytes.Power fails are directly sensed by a built-in power supply monitor, which guards against data loss during transitions from normal operating to power-fail conditions. In order to optimize power sources, this device operates from a single-voltage supply while other devices require a combination of two different voltage levels. It is also available to provide extended temperature range of -40 to 85 degree Celsius as the AT28C64E-12SU version.AT28C64E-12SU is possible to apply to many different fields, such as industrial controllers, digital signal processors (DSPs), digital cameras, medical devices, portable computers and devices utilizing memory cards, automotive systems, network products and embedded controllers.

The basic working principle of AT28C64E-12SU is a self-timed, self-terminated write operation, which starts by sending a control byte containing the start condition, device address bits, read/write control bit, and acknowledgement bit onto the I²C bus. Then, from one to eight data bytes may be written and the Host Controller will provide the stop condition to finish the write operation and end the current transmission.

Technically, the write operation is controlled by three signals: SDA, SCL, and WP. When inputting the control byte, the SDA signal contains both the device address and data; and the SCL signal is used to control the speed at which data is sent. In addition, the WP signal is used to provide a write-protect function. This ensures that no data can be written to protected locations. The erase cycle of AT28C64E-12SU is automatically timed and generated by the assumption that the device holds the current address after power-up.

The erase cycle consists of the following four steps: (1) clearing the data bus, (2) writing 0s to the target location while generating pulses on the SCL and WP signals, (3) driving the SDA signal low during the pulse-on time, and (4) releasing the SCL and WP signals. During the erase operation, a POWER-FAIL reset is triggered, and the write-protect circuitry can also be activated.

To ensure reliable operations, AT28C64E-12SU offers a number of features. One of them is the self-timeout write protect timed. As the device moves from normal operating to power-fail state, the WP function will time out the write command and prevent data corruption. Another is the pulse-width correction circuit, which ensures that valid address information is sent before writing data. This circuit prevents spurious signals from taking erroneously as address signals, thus preventing data corruptions.

In addition to the self-timed write and erase function, AT28C64E-12SU also provides other features such as the shift register sequence read feature. This allows the device to read data in individual bytes with high speed, without the need for additional software. Furthermore, the device can execute a triplet read command, which is useful when reading a series of commands consecutively. The triplet read command allows the device to read a series of bytes with one cycle on the I²C bus, instead of the normal two cycles required.

In conclusion, AT28C64E-12SU is an ideal choice for applications requiring an EEPROM that provides an optimal combination of reliability and low power consumption. With the extended temperature range and the self-terminated write operation, the device is easy to apply to various industrial and embedded applications and provides a high-performance EEPROM solution for engineers.

The specific data is subject to PDF, and the above content is for reference