AT45DB161E-SSHD-B Integrated Circuits (ICs)

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1. Description

The Adesto®AT45DB161E-SSHD-B is a 2.3V or 2.5V minimum, serial-interface sequential access Flash memory ideally suited for a wide variety of digital voice, image, program code, and data storage applications. The AT45DB161E also supports the RapidS serial interface for applications requiring very high speed operation. Its 17,301,504 bits of memory are organized as 4,096 pages of 512 bytes or 528 bytes each. In addition to the main memory, the AT45DB161E also contains two SRAM buffers of 512/528 bytes each. The buffers allow receiving of data while a page in the main memory is being reprogrammed. Interleaving between both buffers can dramatically increase a system's ability to write a continuous data stream. In addition, the SRAM buffers can be used as additional system scratch pad memory, and E2PROM emulation (bit or byte alterability) can be easily handled with a self-contained three step read-modify-write operation. Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the Adesto DataFlash® uses a serial interface to sequentially access its data. The simple sequential access dramatically reduces active pin count, facilitates simplified hardware layout, increases system reliability, minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and industrial applications where high-density, low-pin count, low-voltage, and low-power are essential. To allow for simple in-system re-programmability, the AT45DB161E does not require high input voltages for programming. The device operates from a single 2.3V to 3.6V or 2.5V to 3.6V power supply for the erase and program and read operations. The AT45DB161E is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK). All programming and erase cycles are self-timed.

2. Features

    1. Single 2.3V - 3.6V or 2.5V - 3.6V supply

    2. Serial Peripheral Interface (SPI) compatible

        - Supports SPI modes 0 and 3

        - Supports RapidS™ operation

    3. Continuous read capability through entire array

        - Up to 85MHz

        - Low-power read option up to 15MHz

        - Clock-to-output time (tV) of 6ns maximum

    4. User configurable page size

        - 512 bytes per page

        - 528 bytes per page (default)

        - Page size can be factory pre-configured for 512 bytes

    5. Two fully independent SRAM data buffers (512/528 bytes)

        - Allows receiving data while reprogramming the main memory array

    6. Flexible programming options

        - Byte/Page Program (1 to 512/528 bytes) directly into main memory

        - Buffer Write

        - Buffer to Main Memory Page Program

    7. Flexible erase options

        - Page Erase (512/528 bytes)

        - Block Erase (4KB)

        - Sector Erase (128KB)

        - Chip Erase (16-Mbits)

    8. Program and Erase Suspend/Resume

    9. Advanced hardware and software data protection features

        - Individual sector protection

        - Individual sector lockdown to make any sector permanently read-only

  10. 128-byte, One-Time Programmable (OTP) Security Register

        - 64 bytes factory programmed with a unique identifier

        - 64 bytes user programmable

  11. Hardware and software controlled reset options

  12. JEDEC Standard Manufacturer and Device ID Read

  13. Low-power dissipation

        - 400nA Ultra-Deep Power-Down current (typical)

        - 3µA Deep Power-Down current (typical)

        - 25µA Standby current (typical)

        - 7mA Active Read current (typical @ 15 MHz))

  14. Endurance: 100,000 program/erase cycles per page minimum

  15. Data retention: 20 years

  16. Complies with full industrial temperature range

  17. Green (Pb/Halide-free/RoHS compliant) packaging options

        - 8-lead SOIC (0.150" wide and 0.208" wide)

        - 8-pad Ultra-thin DFN (5 x 6 x 0.6mm)

        - 11-ball Wafer Level Chip Scale Package

        - Die in Wafer Form(1)

3. Pin Configurations

4. Pin description

5. Equipment operation

Device operation is controlled by instructions from the host processor. The edge of CS is followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. Although the CS pin is low, switching the SCK pin controls the opcode and loading of the required buffer or main memory address through the SI (serial input) pin. All instructions, addresses and data use the most important bit (MSB) first. The three address bytes are used to address the buffer area in one of the main memory array or SRAM. The three address bytes will consist of many virtual bits and many actual device addresses. The number of virtual bits depends on the operation being performed and the selected device page size. The buffer addressing of the standard DataFlash page size (528 bytes) uses the terms BFA9-BFA0 in the data sheet to indicate the 10 address bits required to specify the byte address in the buffer. The main memory addressing is referred to by the terms PA11-PA0 and BA9-BA0, where PA11-PA0 represent the 12 address bits required for the specified page address, and BA9-BA0 represent the 10 address bits required for the specified page address. Byte address. Therefore, when using the standard DataFlash page size, there are a total of 22 address bits used. For the "power of two" binary page size (512 bytes), buffer addressing uses the traditional term BFA8-BFA0 in the data table to indicate the nine address bit buffers required to specify a byte address. Main memory addressing is referred to by the terms A20-A0, where A20-A9 represent the bits required by the 12 address to specify the page address, and A8-A0 represent the nine address bits required for the specified byte The address within the page. Therefore, when using the binary page size, a total of 21 address bits are used.

6. Operation Mode Summary

    1. Group A commands consist of:

        - Main Memory Page Read

        - Continuous Array Read (SPI)

        - Read Sector Protection Register

        - Read Sector Lockdown Register

        - Read Security Register

        - Buffer 1 (or 2) Read

    2. Group B commands consist of:

        - Page Erase

        - Block Erase

        - Sector Erase

        - Chip Erase

        - Main Memory Page to Buffer 1 (or 2) Transfer

        - Main Memory Page to Buffer 1 (or 2) Compare

        - Buffer 1 (or 2) to Main Memory Page Program with Built-In Erase

        - Buffer 1 (or 2) to Main Memory Page Program without Built-In Erase

        - Main Memory Page Program through Buffer 1 (or 2) with Built-In Erase

        - Main Memory Byte/Page Program through Buffer 1 without Built-In Erase

        - Auto Page Rewrite

    3. Group C commands consist of:

        - Buffer 1 (or 2) Write

        - Status Register Read

        - Manufacturer and Device ID Read

    4. Group D commands consist of:

        - Erase Sector Protection Register

        - Program Sector Protection Register

        - Sector Lockdown

        - Program Security Register

        - Buffer and Page Size Configuration

        - Freeze Sector Lockdown

7. Package overview