AT45DB321E-SHFHA-T Integrated Circuits (ICs)

description

Adesto®AT45DB321E is a serial interface sequential access flash memory with a minimum of 2.3V, which is very suitable for various digital voice, image, program code and data storage applications. AT45DB321E also supports RapidS serial interface, suitable for applications that require very high-speed operation. Its 34,603,008-bit memory is divided into 8,192 pages in the following way, each with 512 bytes or 528 bytes. In addition to the main memory, the AT45DB321E also contains two SRAM buffers of 512/528 bytes. The buffer allows reprogramming of received data when receiving pages in main memory. Interleaving between the two buffers can significantly improve the system's ability to write continuous data flow. In addition, the SRAM buffer can be used as an additional system scratchpad and E2 PROM emulation (changeability of bits or bytes) can be easily handled through independent three-step read-modify-write operations.

Unlike traditional flash memory, traditional flash memory is randomly accessed through multiple address lines and parallel interfaces.

AdestoDataFlash® uses a serial interface to access its data sequentially. Simple sequential access can significantly reduce the number of effective pins, simplify simplified hardware layout, improve system reliability, minimize switching noise, and reduce package size. The device is optimized for use in many commercial and industrial applications that require high density, low pin count, low voltage, and low power consumption.

In order to achieve simple reprogrammability in the system, AT45DB321E does not require high input voltage to be programmed. The device uses a single 2.3V to 3.6V power supply for erasing, programming and reading operating. AT45DB321E is enabled through the chip select pin (CS) and accessed through the 3-wire interface The relationship between serial input (SI), serial output (SO) and serial clock (SCK).

All program and erase cycles are self-timed.

feature

   1. Single 2.3V - 3.6V supply 

   2. Serial Peripheral Interface (SPI) compatible 

        Supports SPI modes 0 and 3 

        Supports RapidS™ operation 

   3. Continuous read capability through entire array 

        Up to 85MHz 

        Low-power read option up to 15MHz 

        Clock-to-output time (tV) of 6ns maximum 

   4. User configurable page size 

        512 bytes per page 

        528 bytes per page (default) 

        Page size can be factory pre-configured for 512 bytes 

   5. Two fully independent SRAM data buffers (512/528 bytes) 

   6. Flexible programming options 

        Byte/Page Program (1 to 512/528 bytes) directly into main memory 

        Buffer Write 

        Buffer to Main Memory Page Program 

   7. Flexible erase options 

        Page Erase (512/528 bytes) 

        Block Erase (4KB) 

        Sector Erase (64KB) 

        Chip Erase (32-Mbits) 

   8. Program and Erase Suspend/Resume 

   9. Advanced hardware and software data protection features 

        Individual sector protection 

        Individual sector lockdown to make any sector permanently read-only 

 10. 128-byte, One-Time Programmable (OTP) Security Register 

        64 bytes factory programmed with a unique identifier 

        64 bytes user programmable 

 11. Hardware and software controlled reset options 

 12. JEDEC Standard Manufacturer and Device ID Read 

 13. Low-power dissipation 

        400nA Ultra-Deep Power-Down current (typical) 

        3µA Deep Power-Down current (typical) 

        25µA Standby current (typical) 

        11mA Active Read current (typical)

Pin Configurations and Pinouts

Packaging Information