C8051F133-GQR

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1. Analog Peripherals

    1. 10 or 12-bit SAR ADC

        - ± 1 LSB INL 

        - Programmable throughput up to 100 ksps

        - Up to 8 external inputs; programmable as singleended or differential 

        - Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5

        - Data-dependent windowed interrupt generator

        - Built-in temperature sensor

    2. 8-bit SAR ADC (‘F12x Only)

        - Programmable throughput up to 500 ksps 

        - 8 external inputs (single-ended or differential)

        - Programmable amplifier gain: 4, 2, 1, 0.5

    3. Two 12-bit DACs (‘F12x Only)

        - Can synchronize outputs to timers for jitter-free waveform generation

    4. Two Analog Comparators

    5. Voltage Reference

    6. VDD Monitor/Brown-Out Detector

2. On-Chip JTAG Debug & Boundary Scan

    1. On-chip debug circuitry facilitates full-speed, nonintrusive in- circuit/in-system debugging

    2. Provides breakpoints, single-stepping, watchpoints, stack monitor; inspect/modify memory and registers

    3. Superior performance to emulation systems using ICE-chips, target pods, and sockets

    4. IEEE1149.1 compliant boundary scan

    5. Complete development kit

3. 100-Pin TQFP or 64-Pin TQFP Packaging

    1. Temperature Range: –40 to +85 °C

    2. RoHS Available

3. High Speed 8051 µC Core

    1. Pipelined instruction architecture; executes 70% of instruction set in 1 or 2 system clocks

    2. 100 MIPS or 50 MIPS throughput with on-chip PLL

    3. 2-cycle 16 x 16 MAC engine 

4. Memory

    1. 8448 bytes internal data RAM (8 k + 256)

    2. 128 or 64 kB Banked Flash; in-system programmable in 1024-byte sectors

    3. External 64 kB data memory interface (programmable multiplexed or non-multiplexed modes)

5. Digital Peripherals

    1. 8 byte-wide port I/O (100TQFP); 5 V tolerant

    2. 4 Byte-wide port I/O (64TQFP); 5 V tolerant

    3. Hardware SMBus™ (I2C™ Compatible), SPI™, and two UART serial ports available concurrently

    4. Programmable 16-bit counter/timer array with 6 capture/compare modules

    5. 5 general purpose 16-bit counter/timers

    6. Dedicated watchdog timer; bi-directional reset pin

6. Clock Sources

    1. Internal precision oscillator: 24.5 MHz

    2. Flexible PLL technology

    3. External Oscillator: Crystal, RC, C, or clock

7. Voltage Supples

    1. Range: 2.7–3.6 V (50 MIPS) 3.0–3.6 V (100 MIPS)

    2. Power saving sleep and shutdown modes

8. Additional Features

Several key enhancements are implemented in the CIP-51 core and peripherals to improve overall performance and ease of use in end applications. The extended interrupt handler provides 20 interrupt sources into the CIP-51 (as opposed to 7 for the standard 8051), allowing the numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when building multi-tasking, real-time systems. There are up to seven reset sources for the MCU: an on-board VDD monitor, a Watchdog Timer, a missing clock detector, a voltage level detection from Comparator0, a forced software reset, the CNVSTR0 input pin, and the RST pin. The RST pin is bi-directional, accommodating an external reset, or allowing the internally generated POR to be output on the RST pin. Each reset source except for the VDD monitor and Reset Input pin may be disabled by the user in software; the VDD monitor is enabled/disabled via the MONEN pin. The Watchdog Timer may be permanently enabled in software after a power-on reset during MCU initialization. The MCU has an internal, stand alone clock generator which is used by default as the system clock after any reset. If desired, the clock source may be switched on the fly to the external oscillator, which can use a crystal, ceramic resonator, capacitor, RC, or external clock source to generate the system clock. This can be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) external crystal source, while periodically switching to the 24.5 MHz internal oscillator as needed. Additionally, an on-chip PLL is provided to achieve higher system clock speeds for increased throughput.