ATTINY1604-SSF

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1. Describe

The ATtiny804/1604 microcontrollers feature a high-performance, low-power AVR® RISC architecture capable of operating at up to 20 MHz, with up to 8/16 KB of Flash, 512/1024 bytes of SRAM and 128/256 bytes of SRAM EEPROM in a 14-pin package. The family uses the latest technology and flexible low-power architecture, including event system and SleepWalking, accurate analog functions and advanced peripherals.

2. Features

    1. CPU:

        – AVR® 8-bit CPU

        – Running at up to 20 MHz

        – Single cycle I/O access

        – Two-level interrupt controller

        – Two-cycle hardware multiplier

    2. Memories:

        – 8/16 KB In-system self-programmable Flash memory

        – 128/256B EEPROM

        – 512/1024B SRAM

    3. System:

        – Power-on Reset (POR)

        – Brown-out Detection (BOD)

        – Internal and external clock options with:

           16/20 MHz low-power internal RC oscillator

           32.768 kHz Ultra Low Power (ULP) internal RC oscillator with ±10% accuracy, ±2% calibration step size

           External clock input

        – Single pin Unified Program Debug Interface (UPDI)

        – Three sleep modes:

           Idle with all peripherals running and mode for immediate wake-up time

           Standby Sleep mode:

           1. Configurable operation of selected peripherals

           2. SleepWalking peripherals

    4. Power-Down Sleep mode with limited wake-up functionality

    5. Peripherals:

        – 3-channel Event System

        – One 16-bit Timer/Counter with Dedicated Period register and Three Compare Channels (TCA)

        – One 16-bit Timer/Counter type B with Input Capture (TCB)

        – One 16-bit Real Time Counter (RTC) running from internal RC oscillator

        – One USART with fractional baud rate generator, auto-baud, Start-Of-Frame (SOF) detection, and Local Interconnect Network (LIN) support

        – Master/slave Serial Peripheral Interface (SPI)

        – Master/slave TWI with dual address match

           Standard mode (Sm, 100 kHz)

           Fast mode (Fm, 400 kHz)

           Fast mode Plus (Fm+, 1 MHz)

        – Configurable Custom Logic (CCL) with two Programmable Lookup Tables (LUT)

        – One Analog Comparator (AC) with 150 ns propagation delay

        – 10-bit 115ksps Analog-to-Digital Converter (ADC)

        – Five selectable internal voltage references: 0.55V, 1.1V, 1.5V, 2.5V and 4.3V

        – Automated CRC memory scan

        – Programmable Watchdog Timer (WDT) with separate on-chip oscillator

        – External interrupt on all general purpose pins

    6. I/O and Packages:

        – 14-pin

           12 Programmable I/O lines

           SOIC150

    7. Temperature Ranges:

        – -40°C to 105°C operating range

        – -40°C to 125°C temperature graded device options available

    8. Speed Grades:

        – TA max. 105°C

           0-5 MHz @ 1.8V – 5.5V

           0-10 MHz @ 2.7V – 5.5V

           0-20 MHz @ 4.5V – 5.5V

3. Arithmetic Logic Unit (ALU)

The Arithmetic Logic Unit (ALU) supports arithmetic and logical operations between registers or between constants and registers. Additionally, single-register operations can be performed. The ALU is directly connected to all 32 general purpose registers. Arithmetic operations between general purpose registers or between registers and immediate values are performed in a single clock cycle and the results are stored in a register file. After an arithmetic or logical operation, the status register (CPU.SREG) is updated to reflect information about the result of the operation. ALU operations fall into three broad categories—arithmetic, logical, and bit functions. Both 8-bit and 16-bit arithmetic are supported, and the instruction set allows efficient implementation of 32-bit arithmetic. Hardware multiplier supports signed and unsigned multiplication and fractional formats

4. Procedure flow chart

After reset, the CPU will execute instructions from the lowest address of Flash program memory at 0x0000. The program counter (PC) addresses the next instruction to be fetched. Program flow is supported by conditional and unconditional JUMP and CALL instructions, capable of directly addressing the entire address space. Most AVR instructions use a 16-bit word format, and a few use a 32-bit format. During interrupts and subroutine calls, the return address PC is stored on the stack as a word pointer. The stack is allocated in general-purpose data SRAM, so the stack size is only limited by the total SRAM size and SRAM usage. After reset, the Stack Pointer (SP) points to the highest address in the internal SRAM. The SP has read/write access in the I/O memory space, making it easy to implement multiple stacks or stack regions. The data SRAM can be easily accessed through five different addressing modes supported by the AVR CPU.

5. stack and stack pointer

The stack is used to store return addresses after interrupts and subroutine calls. Also, it can be used to store temporary data. The stack pointer (SP) always points to the top of the stack. SP is defined by the stack pointer bits in the stack pointer register (CPU.SP). CPU.SP is implemented as two 8-bit registers, accessible in the I/O memory space. Use the PUSH and POP instructions to push and pop data from the stack. The stack grows from higher memory locations to lower memory locations. This means that pushing data onto the stack lowers SP, and popping data off the stack increases SP. The stack pointer is automatically set to the highest address of the internal SRAM after reset. If the stack changes, it must be set to point above address 0x2000, and it must be defined before any subroutine calls are performed and interrupts are enabled. During an interrupt or subroutine call, the return address is automatically pushed onto the stack as a word pointer, and the SP is decremented by 2. The return address consists of two bytes, the least significant byte is pushed onto the stack first (at the higher address).

6. Access 16-bit registers

The AVR data bus is 8 bits wide, so accessing 16-bit registers requires atomic operations. These registers must be byte accessed using two read or write operations. 16-bit registers are connected to an 8-bit bus and scratch registers that use a 16-bit bus. For write operations, the low byte of the 16-bit register must be written before the high byte. Then write the low byte to the scratch register. When the high byte of the 16-bit register is written, the temporary register is copied to the low byte of the 16-bit register in the same clock cycle. For read operations, the low byte of the 16-bit register must be read before the high byte. When the CPU reads the low byte register, the high byte of the 16-bit register is copied into the scratch register in the same clock cycle as the low byte is read. When reading the high byte, read from the scratch register. This ensures that the low and high bytes of the 16-bit register are always accessed simultaneously when the register is read or written. If an interrupt is triggered during an atomic 16-bit read/write operation and the same 16-bit register is accessed, the interrupt can corrupt timing. To prevent this, interrupts can be disabled when writing or reading 16-bit registers.

7. Programming

For page programming, filling the page buffer and writing the page buffer into Flash, User Row, and EEPROM are two separate operations.  Before programming a Flash page with the data in the page buffer, the Flash page must be erased. The page buffer is also erased when the device enters a sleep mode. Programming an unerased Flash page will corrupt its content. The NVM command set supports both a single erase and write operation, and split Page Erase and Page Write commands. This split commands enable shorter programming time for each command, and the erase operations can be done during non-time-critical programming execution. The EEPROM programming is similar, but only the bytes updated in the page buffer will be written or erased in the EEPROM.

8. Commands

Reading of the Flash/EEPROM and writing of the page buffer is handled with normal load/store instructions. Other operations, such as writing and erasing the memory arrays, are handled by commands

in the NVM.

9. Write Command

The Write command of the Flash controller writes the content of the page buffer to the Flash or EEPROM. If the write is to the Flash, the CPU will stop executing code as long as the Flash is busy with the write operation. If the write is to the EEPROM, the CPU can continue executing code while the operation is ongoing. The page buffer will be automatically cleared after the operation is finished.

10. Erase Command

The Erase command erases the current page. There must be one byte written in the page buffer for the Erase command to take effect. For erasing the Flash, first, write to one address in the desired page, then execute the command. The whole page in the Flash will then be erased. The CPU will be halted while the erase is ongoing. For the EEPROM, only the bytes written in the page buffer will be erased when the command is executed. To erase a specific byte, write to its corresponding address before executing the command. To erase a whole page all the bytes in the page buffer have to be updated before executing the command. The CPU can continue running code while the operation is ongoing. The page buffer will be automatically cleared after the operation is finished.