CD4555BPW

Logic - Signal Switches, Multiplexers, Decoders

CD4555BPW application field and working principle

The CD4555BPW (CMOS Dual 1-of-4 Decoder/Non-Inverting Data Selector) is a combination of two (1-of-4) decoders and two (non-inverting) data selectors. The two decoders take an active-low pair of selection inputs, A and B, together with an active-high Enable input (E), and simultaneously activate one of four active-low outputs, Q0 to Q3. The two data selectors take two active-low data inputs, D0 and D1, and selection inputs A, B, and E, and simultaneously drive one of four data outputs, Y0 to Y3 with inverted logic level functions of the data inputs. When Enable is low, all output drivers are off.

Features

• Wide Operating Supply Voltage - VDD = 5V to 18V
• InputsTolerant to 18V (except Enable)
• Fail-Safe Protection in the Event of an Overvoltage Input
• High Noise Immunity
• Very Low Quiescent and Standby Power Consumption
• Open-Drain Outputs for Improving Latch-up Immunity
• Improved Noise Margin of Outputs

Applications

The CD4555BPW can be used in a variety of applications such as logic level conversion, system logic and addressing, logic switching and digital signal routing. It is also used in multiplexers, decoders, signal routing, and interfaces. It can be used as an addressing/switching signal block or an input/output translator that have no unequal outputs when the input is in a logic low state. In addition, this integrated circuit is used in ROM addressing, signal line sensing, and in low-power linear logic circuits.

Working Principle

The CD4555BPW (CMOS Dual 1-of-4 Decoder/Non-Inverting Data Selector) operates in two stages. The first stage consists of two (1-of-4) decoders and the second stage consists of two (non-inverting)data selectors. The two decoders enable one of the four active-low outputs (Q0 to Q3) when it receives an active-low selection pair of inputs (A and B) together with an active-high Enable input (E). The two data selectors simultaneously drive one of four data outputs (Y0 to Y3) with inverted logic level functions of the data inputs (D0 and D1). When Enable is low, all output drivers are off.

The CD4555BPW is an integrated device containing four digital logic elements in a single package. Its logic elements are optimised for operation from 5V to 18V power supply and feature a wide range of temperature, voltage and frequency tolerant inputs. The device contains high-speed outputs with good noise immunity and high data retention. The CMOS dual 1-of-4 decoder/non-inverting data selector can be used in a variety of applications such as logic level conversion, system logic and addressing, logic switching and digital signal routing.