Allicdata Part #: | CDC5806PWRG4-ND |
Manufacturer Part#: |
CDC5806PWRG4 |
Price: | $ 0.00 |
Product Category: | Integrated Circuits (ICs) |
Manufacturer: | Texas Instruments |
Short Description: | IC CLOCK GEN PLL 3.3V 20TSSOP |
More Detail: | N/A |
DataSheet: | CDC5806PWRG4 Datasheet/PDF |
Quantity: | 1000 |
1 +: | 0.00000 |
Specifications
Differential - Input:Output: | No/No |
Base Part Number: | CDC5806 |
Supplier Device Package: | 20-TSSOP |
Package / Case: | 20-TSSOP (0.173", 4.40mm Width) |
Mounting Type: | Surface Mount |
Operating Temperature: | -40°C ~ 85°C |
Voltage - Supply: | 3 V ~ 3.6 V |
Divider/Multiplier: | Yes/No |
Frequency - Max: | 74MHz |
Series: | -- |
Ratio - Input:Output: | 1:6 |
Number of Circuits: | 1 |
Output: | LVCMOS, LVTTL |
Input: | LVCMOS, LVTTL |
PLL: | Yes with Bypass |
Type: | PLL Clock Generator |
Part Status: | Obsolete |
Packaging: | Tape & Reel (TR) |
Description
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The CDC5806PWRG4 by Texas Instruments is a differential-output, buffer-and-driver device that generates high-frequency, low-skew, low-noise differential clocks. It provides a spread-spectrum-compliant differential output solution with support for a wide range of LVPECL, LVDS, HSTL and CML differential output standards. This device is ideal for applications requiring precise control of the output skew or noise reduction. This product is classified in Clock / Timing - Clock Generators,PLLs, Frequency Synthesizers.CDC5806PWRG4 Application FieldThe CDC5806PWRG4 is designed to reduce jitter in high-speed clock signals distributed in a system. The output-clock signals are demultiplexed from high-frequency reference clocks and can be used to provide 2.5 GHz clock-signal distribution. Common applications of these devices include servers and processor-based systems. They can also be used in other communication systems that require buffered differential clock-signal distribution.CDC5806PWRG4 Working PrincipleThe CDC5806PWRG4 is a differential-output, buffer-and-driver device that generates high-frequency, low-skew, low-noise differential clocks. It contains an integrated non-resonant voltage-controlled oscillator (VCO), reference-clock selector, base-frequency generator, and two banks of zero-skew buffers. The VCO is designed to generate a range of output frequencies from 2.5 Gen/s to 3.8 Gen/s. The device\'s internal reference-clock selector enables the user to select from three reference-clock inputs: an external reference clock, a configurable PPS reference clock, or an onboard reference oscillator. The configurable PPS reference clock enables users to input an external reference clock with a frequency between 250 MHz and 1.1 GHz.The device also contains two base-frequency generators. The first is designed to receive an external input reference clock with a frequency between 75 MHz and 1100 MHz. This input clock is then divided by a programmablemdivider to generate a base frequency of 25 MHz, 50 MHz, or 100 MHz through a 0.25 GHz to 1.1 GHz input. The second base-frequency generator is used to generate a local reference clock with a frequency of 25 MHz, 50 MHz, or 100 MHz. The local reference automatically synchronizes to an external reference clock, if a reference clock is present.The device\'s two banks of zero-skew buffers enable users to select up to two differential clock outputs with the same frequency but with opposite polarities. They are designed to minimize output skew and to reduce noise on the clock-signal inputs. The outputs of the device can be programmed for a variety of different LVPECL, LVDS, HSTL, and CML standards.The CDC5806PWRG4 can be used in a variety of systems requiring constant, low-skew, low-noise clock-signal distribution. The device provides a spread-spectrum-compliant differential output solution with support for a wide range of LVPECL, LVDS, HSTL and CML differential output standards. It is designed to provide reliable clock signals over wide temperature ranges, ensuring consistent performance over time.ConclusionThe CDC5806PWRG4 is a differential-output, buffer-and-driver device that is capable of generating high-frequency, low-skew, low-noise clock signals. It contains an integrated non-resonant voltage-controlled oscillator, reference-clock selector, two banks of zero-skew buffers and two base-frequency generators. The device can be configured to provide output frequencies of 2.5 Gen/s to 3.8 Gen/s. The device can be used to reduce jitter in clock-signal distribution in a variety of systems requiring low-skew, low-noise clock signals.The specific data is subject to PDF, and the above content is for reference
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