DAC8775IRWFR

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1. Describe

The DAC8775IRWFR is a quad-channel precision, fully Integrated 16-bit digital-to-analog converter (DAC) Features adaptive power management, designed to Meet industrial control requirements application. Adaptive Power Management circuit, when enabled, minimizes power dissipation of the chip. when programmed as Current output, current supply voltage Output driver regulated between 4.5 V and 32 V Voltage-Based Continuous Feedback Current output pin via integrated buck/boost converter. When programmed as a voltage output, This circuit generates a programmable supply voltage For voltage output stage (±15 V). DAC8775 also Contains an LDO to generate digital power (5 V) from a single supply pin. The DAC8775IRWFR is also implemented using the highway Addressable Remote Transducer (HART) Signal Interface for superimposing external HART signals current output. Slew rate of current output The DAC is register programmable. The device can Powered by a single external supply of +12 V Use Integrated Buck/Boost Converter to +36 V or use an external power supply when buck/boost Converter is disabled.

2. Feature

    1. Output current:

        – 0 mA to 24 mA; 3.5 mA to 23.5 mA; 0 mA to 20 mA; 4 mA to 20 mA; ±24 mA

    2. Output voltage (with/without 20% overrange):

        – 0 V to 5 V; 0 V to 10 V; ±5V; ±10 V

        – 0 V to 6 V; 0 V to 12 V; ±6V; ±12 V

    3. Adaptive power management

    4. Single-width power pins (12 V – 36 V)

    5. ±0.1% FSR Total Unadjusted Error (TUE)

    6. DNL: ±1 LSB max

    7. Internal 5V reference voltage (10 ppm/°C max)

    8. Internal 5V digital power output

    9. CRC/frame error checking, watchdog timer

  10. Thermal alarm, open/short to ensure system reliability

  11. Safety measures under alarm conditions

  12. Automatic learning load detection

  13. Wide temperature range: –40°C to +125°C

3. Application

    1. 4mA to 20mA current loop

    2. Analog output modules

    3. Programmable Logic Controller (PLC)

    4. Building automation

    5. Sensor transmitter

    6. Process control

4. Pin configuration

5. Buck-Boost Converter Output

Each of the four buck-boost converters can be used to power either a current output stage or a voltage output stage by enabling the corresponding buck-boost converter and connecting the power supply. Optionally add additional passive filters between the Schottky diodes and the input supply pins (VPOS_IN_x and VNEG_IN_x) to attenuate the ripple fed into the VPOS_IN_x and VNEG_IN_x pins.

6. Selecting and Enabling Buck-Boost Converters

The analog outputs of the Buck-Boost converters can be enabled in two different ways: Current Output Mode or Voltage Output Mode. Any and all combination of the DAC8775 Buck-Boost converters can be selected by writing to address 0x06 . The positive/negative arm of the selected Buck-Boost converter can be enabled via writing to address 0x07 . Note that, VNEG_IN_x is internally shorted to PBKG when the negative arm of Buck-Boost converter is not enabled. When used in voltage output mode, the Buck-Boost converter generates a constant ±15.0 V for the positive and negative power supplies. Alternatively this constant voltage may be modified by the clamp register setting for each channel. When used in current output mode the Buck-Boost converter generates the positive and negative power supply based on the RANGE setting, for example the negative power supply is only generated for ±24 mA range. The minimum voltage that the Buck-Boost converter can generate on the VPOS_IN_x pin in 4.96 V with a typical efficiency of 75% at PVDD_x = 12 V and a load current of 24 mA, thus significantly minimizing power dissipation on chip. The maximum voltage that the Buck Boost converter can generate on the VPOS_IN_x pin is 32 V. Similarly, the minimum voltage that the Buck-Boost converter can generate on the VNEG_IN_x pin in –18.0 V. The maximum voltage that the Buck-Boost converter can generate on the VNEG_IN_x pin in –5.0 V.

7. Analog Power Supply

After power up it is required that a hardware reset is issued using the RESET pin. The DAC8775 is design to operate with a single power supply (12 V to 36 V) using integrated Buck-Boost converter. In this mode, pins PVDD_x and AVDD must be tied together and driven by the same power supply. VPOS_INx and VNEG_IN_x will be enabled as programmed by the device registers. It is recommended that DVDD is applied first to reduce output transients. The DAC8775 can also be operated without using the integrated Buck-Boost converter. In this mode, pins PVDD_x, AVDD, and VPOS_IN_x must be tied together and driven by the same power supply (12 V to 36 V). In this mode in order to reduce output transients it is recommended that DVDD is applied first, followed by VPOS_IN_x / PVDD_x / AVDD and finally REFIN. Note that in this mode, the minimum required head room and foot room for the output amplifiers must be met.

8. Digital Power Supply

The digital power supply to DAC8775 can be internally generated or externally supplied. This is determined by the status of DVDD_EN pin. When the DVDD_EN pin is left floating, the voltage on DVDD pin is generated via a ernal LDO. The typical value of the voltage generated on DVDD pin is 5 V. In this mode, the DVDD pin can also be used to power other digital components on the board. The maximum drive capability of this pin is 10mA. Please note that to ensure stability the minimum load capacitance on this pin is limited to 100 pF, where as the maximum load capacitance is limited to 0.1 µF. When the DVDD_EN pin is tied to 0 V, the internal LDO is disabled and the DVDD pin must be powered via an external digital supply.

9. Power-On-Reset

The DAC8775 contain power on reset circuits which is based on AVDD and DVDD power supplies. After poweron, the power-on-reset circuit ensures that all registers are at their default values . The current, voltage output DACs, and the Buck-Boost converters are disabled. The current output pin is in high impedance state. The voltage output pin is in a 30kΩ-to-GND state; however, the VSENSEP_x pin is an open circuit. The voltage output pin impedance may be changed to high-impedance by the POC bit setting.

10. Serial Peripheral Interface (SPI)

The device is controlled over a versatile four-wire serial interface (SDIN, SDO, SCLK, and SYNC) that operates at clock rates of up to 25 MHz and is compatible with SPI, QSPI™, Microwire™, and digital signal processing (DSP) standards. The SPI communication command consists of a write address byte and a data word for a total of 24 bits (when CRC is disabled). The timing for the digital interface is shown in the Timing Requirements: Write and Readback Mode section.

11. Stand-Alone Operation

The serial clock SCLK can be a continuous or a gated clock. When SYNC is high, the SCLK and SDIN signals are blocked and the SDO pin is in a HiZ state. Exactly 24 falling clock edges must be applied before SYNC is brought high. If SYNC is brought high before the 24th falling SCLK edge, then the data written are not transferred into the internal registers. If more than 24 falling SCLK edges are applied before SYNC is brought high, then the last 24 bits are used. The device internal registers are updated from the Shift Register on the rising edge of SYNC. In order for another serial transfer to take place, SYNC must be brought low again.