Allicdata Part #: | DS21600SN+-ND |
Manufacturer Part#: |
DS21600SN+ |
Price: | $ 0.00 |
Product Category: | Integrated Circuits (ICs) |
Manufacturer: | Maxim Integrated |
Short Description: | IC ADAPT CLK RATE 3.3V/5V 16SOIC |
More Detail: | N/A |
DataSheet: | DS21600SN+ Datasheet/PDF |
Quantity: | 1000 |
1 +: | 0.00000 |
Specifications
Series: | -- |
Packaging: | Tube |
Part Status: | Obsolete |
Type: | Clock Rate Adapter |
PLL: | Yes |
Input: | Clock |
Output: | Clock |
Number of Circuits: | 1 |
Ratio - Input:Output: | 1:2 |
Differential - Input:Output: | No/No |
Frequency - Max: | 6.176MHz |
Divider/Multiplier: | Yes/No |
Voltage - Supply: | 3.135 V ~ 5.25 V |
Operating Temperature: | -40°C ~ 85°C |
Mounting Type: | Surface Mount |
Package / Case: | 16-SOIC (0.295", 7.50mm Width) |
Supplier Device Package: | 16-SOIC |
Base Part Number: | DS21600 |
Description
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DS21600SN+ Application Field and Working PrincipleThe DS21600SN+ is an ultra-low jitter, high performance clock generator developed by Dallas Semiconductor Corporation. This device combines a low-noise oscillator, an advanced Phase-Lock Loop (PLL) and an adjustable output buffer to produce a wide range of clock frequencies. It is used in many application fields, including network and communications systems, broadcast systems, or any application requiring low jitter and high frequency clock generation. The DS21600SN+ contains two independent output buffers, each of which can be configured to produce clocks from DC to approximately 350MHz. Using PLL techniques, it is possible to achieve frequency translation while preserving the low jitter characteristics of the oscillator and PLL. By default, each output buffer has a selectable divide-by-one, divide-by-two, and divide-by-four ratio. Custom configurations are also available to allow for fine-tuning of the output frequency. When used as a clock generator, the DS21600SN+ produces a low noise and low jitter signal output. This is accomplished by first inputting an external crystal oscillator signal. The signal, depending on the voltage level, is then amplified and filtered, and sent to the PLL circuit. The PLL consists of a phase detector, a loop filter and a voltage-controlled oscillator (VCO). The PLL then computes the ratio of the incoming crystal reference frequency and the desired clock rate, and tunes the VCO accordingly. The output of the PLL is then filtered by an output buffer prior to being sent to the user. This enables the user to set exactly the desired frequency at the output pin. In summary, the DS21600SN+ is an advanced performance clock generator developed by Dallas Semiconductor Corporation. It is ideal for applications where low jitter and high frequency clock generation are required. The device operates by first inputting an external reference signal and then computing the ratio of the reference frequency and the desired clock rate. The output of the PLL is then filtered by an output buffer prior to being sent to the user. This enables users to achieve a wide range of clock frequencies while preserving the low jitter characteristics of the oscillator and PLL.The specific data is subject to PDF, and the above content is for reference
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