Allicdata Part #: | GAL26V12C-20LJ-ND |
Manufacturer Part#: |
GAL26V12C-20LJ |
Price: | $ 0.00 |
Product Category: | Integrated Circuits (ICs) |
Manufacturer: | Lattice Semiconductor Corporation |
Short Description: | IC CPLD 12MC 20NS 28PLCC |
More Detail: | N/A |
DataSheet: | GAL26V12C-20LJ Datasheet/PDF |
Quantity: | 1000 |
Series: | GAL®26V12 |
Packaging: | Tube |
Part Status: | Obsolete |
Programmable Type: | EE PLD |
Delay Time tpd(1) Max: | 20.0ns |
Voltage Supply - Internal: | 4.75 V ~ 5.25 V |
Number of Macrocells: | 12 |
Operating Temperature: | 0°C ~ 75°C (TA) |
Mounting Type: | Surface Mount |
Package / Case: | 28-LCC (J-Lead) |
Supplier Device Package: | 28-PLCC (11.51x11.51) |
Base Part Number: | GAL26V12 |
Due to market price fluctuations, if you need to purchase or consult the price. You can contact us or emial to us: sales@allicdata.com
GAL26V12C-20LJ is a member of a family of embedded-CPLDs (Complex Programmable Logic Devices). It is specifically developed for applications demanding low power, high performance and ease of use. GAL26V12C-20LJ\'s non-volatile architecture offers exceptional system capabilities in terms of power, performance, cost and time savings.
The device includes 36 macrocells with 16-bit wide configurable logic array, 2.18 I/O (input/output) pins, five independent clocks and supports LVTTL, LVCMOS, TTL and HCMOS logic families. It offers a wide range of features such as high speed D-type flip-flops, dual configurable data latches, support for multi-way devices and a configurable embedded ROM.
GAL26V12C-20LJ is suitable for data processing and processing of real-time events, where high performance and low power consumption are essential. It is uniquely suited for applications like automotive, medical, industrial and communication systems that require performance and low power consumption. The device also offers excellent system integration capabilities and can be used for the implementation of complex logic functions.
The principal of operation of GAL26V12C-20LJ is based on field-programmable logic array (FPLA) technology. The device includes macrocells with 16-bit wide configurable logic blocks that are arranged in a matrix formation. Each FPLA chip can be reconfigured in order to implement a specific logic function using a configuration file that is loaded into the device. The configuration file contains the logic information needed to define the logic blocks and their interconnections. Depending on the application requirements, the number of FPLAs can be increased or decreased.
The GAL26V12C-20LJ operates in two mode, sequencer and test mode. In the sequencer mode, the FPLAs are configured according to the logic of the application. This mode is mainly used for applications involving data processing and software execution. In the test mode, the FPLAs are configured for testing, debugging and fault detection.
The GAL26V12C-20LJ provides excellent system integration capabilities and is used by many manufacturers for high-end system design. It is an ideal choice for applications requiring high performance, low power and excellent system integration.
The specific data is subject to PDF, and the above content is for reference
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