M4A5-192/96-7VNC

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1. DESCRIPTION

The ispMACH™ 4A family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The ispMACH 4A devices offer densities ranging from 32 to 512 macrocells with 100% utilization and 100% pin-out retention. The ispMACH 4A families offer 5-V (M4A5- xxx) and 3.3-V (M4A3-xxx) operation. ispMACH 4A products are 5-V or 3.3-V in-system programmable through the JTAG (IEEE Std. 1149.1) interface. JTAG boundary scan testing also allows product testability on automated test equipment for device connectivity. All ispMACH 4A family members deliver First-Time-Fit and easy system integration with pin-out retention after any design change and refit. For both 3.3-V and 5-V operation, ispMACH 4A products can deliver guaranteed fixed timing as fast as 5.0 ns tPD and 182 MHz fCNT through the SpeedLocking feature when using up to 20 product terms per output (Table 2).

2. FEATURES

    1. High-performance, E2 CMOS 3.3-V & 5-V CPLD families

    2. Flexible architectu  re for rapid logic designs

        — Excellent First-Time-FitTM and refit feature

        — SpeedLockingTM performance for guaranteed fixed timing

        — Central, input and output switch matrices for 100% routability and 100% pin-out retention

    3. High speed

        — 5.0ns tPD Commercial and 7.5ns tPD Industrial

        — 182MHz fCNT

    4. 32 to 512 macrocells; 32 to 768 registers

    5. 44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages

    6. Flexible architecture for a wide range of design styles

        — D/T registers and latches

        — Synchronous or asynchronous mode

        — Dedicated input registers

        — Programmable polarity

        — Reset/ preset swapping

    7. Advanced capabilities for easy system integration

        — 3.3-V & 5-V JEDEC-compliant operations

        — JTAG (IEEE 1149.1) compliant for boundary scan testing

        — 3.3-V & 5-V JTAG in-system programming

        — PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)

        — Safe for mixed supply voltage system designs

        — Programmable pull-up or Bus-FriendlyTM inputs and I/Os

        — Hot-socketing

        — Programmable security bit

        — Individual output slew rate control

    8. Advanced E2 CMOS process provides high-performance, cost-effective solutions

    9. Lead-free package options

3. Pin configuration