M86201G12

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The M86201G12 is an FPGA based High-Speed Synchronous Optical Network (SONET/SDH) core, designed to interface a SONET/SDH network to any of a variety of existing and emerging Asynchronous Transfer Mode (ATM) systems. It provides an easy-to-implement, low cost, flexible and interoperable solution for synchronous networks. The M86201G12 is a highly integrated solution for synchronous data transport from M/E (2Mbps) to STS/OC3 (150Mbps) and STS/OC48 (2.5Gbps).

The M86201G12 can be used to connect between 2 different networks, such as ATM and SONET/SDH networks, or SONET/SDH networks with different speeds. This core provides an efficient interface and a reliable connection, enabling broadcast and multicast of SONET/SDH signals, allowing SONET/SDH channels to be mapped directly into ATM cells. The M86201G12 simplifies the design of ATM switches and helps reduce the system latency due to its optimized memory architecture.

The M86201G12 core is designed to reduce the time to market, enabling the development of products that incorporate SONET/SDH link layer processing with minimal cost, time and engineering effort. The M86201G12 can be used for applications such as access networks, transport networks, datacom and telecom, and test equipment. The core can also be used in Wireless 4G core networks, Digital Video Broadcasting (DVB-C), and Packet Cable solutions.

The M86201G12 provides the following features:

• Compliant with SONET/SDH standards, including OC3-STM1, OC12-STM4, and OC48-STM16
• Single/Dual port selectable TX/RX/Evenodd
• Automatic loopback testing and monitor mode selection
• Flexible Virtual Concatenation
• At-speed scrambling/descrambling
• Supports 16-bit, 8-bit, or dual-byte scan interface
• Integrated error checking/correction for CRC, NCC, PAAL, SPI4.2 and RS/FEC
• Embedded 8-bit HDLC processor

The M86201G12 core provides a complete solution for the physical and link layers of SONET/SDH networks. The core is designed to implement layer two functions in hardware, while allowing the control layer to access data on the physical layer through an Application Programming Interface (API).

The core consists of an FPGA-based physical layer and a link layer. The physical layer handles all the traditional SONET/SDH operations such as bit/frame synchronization, error detection, monitoring and signaling. The link layer is responsible for the higher-level operations such as encoding, decoding, addressing and error control. The two layers are connected through the SPI4.2 interface to the control layer.

The core has an asynchronous interface, enabling it to integrate easily with any existing interface. The M86201G12 can also interface to other system components through its built-in HDLC protocol engine. It is designed to support up to two simultaneous ports, allowing the system designer to increase throughput while minimizing core size.

The M86201G12 is flexible and easy to use, enabling the development of efficient and cost-effective solutions for high-speed communication interface applications. Using the M86201G12 core, system developers can quickly and easily design a variety of innovative and reliable products for access networks, transport networks, datacom and telecom, and test equipment.

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