MAX6796TPLD0+

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The MAX6796TPLD0+ is a member of the supervisory circuits family in PMIC (Power Management Integrated Circuits). It is a low-power, high-precision 3 V/5 V reset supervisor designed to monitor and control power-on reset (POR) conditions. It provides a minimum reset voltage window detecting levels as low as 2.30 V (100 mV below the current VDD threshold below which the device operates in low-power state). It can also provide an output voltage window down to 1.6 V.

A key feature of the MAX6796TPLD0+ is its ability to detect and reset multiple power sources when wired in a daisy chain. It supports reset signaling from the MAX6796 devices across multiple power supplies or supplies with varying voltages. The MAX6796TPLD0+ provides data hold capabilities to ensure correct reset information is latched and reset signals are propagated even when the power is off.

The MAX6796TPLD0+ also offers reset monitoring with adjustable debounce circuits and output pulse widths. It is ideal for any application where detection of low voltage and fast reset signals is critical, such as in board-level reset controllers. The device can detect multiple power sources and enforces that each source passes a minimum valid reset voltage before releasing a reset signal. It also supports pulse frequency limiting, which helps reduce system noise caused by erroneous reset signals.

The MAX6796TPLD0+ is available in a thermally enhanced TPLD (34-pin) package for a wide-range industrial temperature range of -40°C to +85°C. It is characterized for operation from a supply voltage of 1.5 V to 5.5 V and is available in both a small-footprint, 8-pin SOIC package and a 4-pin SOT-23 package for lower-power applications.

The MAX6796TPLD0+ consists of two integrated analog comparators. The non-inverting input references an internal 2.3 V threshold with a 30 mV hysteresis whereas the inverting input is set to 0.75 V. The comparators provide an active-LOW output, RESET, to signal a valid reset. The RESET output remains active until the non-inverting input returns above the 2.6 V threshold or until it is debounced. The debounce period can be internally adjusted with the DEB pin.

The MAX6796TPLD0+ also includes configurable logic that allows for both manual and automatic reset modes. In manual reset mode, manual reset conditions are set by the user. If the DEB pin is left unconnected, the reset events will be latched and the reset will remain active until the reset condition is cleared. In automatic reset mode, the MAX6796TPLD0+ monitors reset flags on the Reset Input pin and if a valid reset is detected, the RESET output is asserted and held active until the RESET pin returns to its inactive state.

The device also has adjustable power-on reset (POR) time intervals, which are settable using a selector pin called the PWR_UP. The PWR_UP pin accepts a logic 0 to indicate that the device is powered, and when set to 0, the device monitors the RESET pin for incoming reset signals. The PWR_up pin is powered off when the device is removed from the system. This feature helps prevent erroneous reset signals from occurring after reset conditions have been cleared.

The MAX6796TPLD0+ includes a Watchdog Timer (WDT) for safely restarting a system in the event that it becomes unresponsive. In manual reset mode, the WDT can be enabled by connecting the WDT pin to VDD. The WDT monitors valid reset pulses on the RESET pin and will assert a reset when pulses are not detected during the programmable timeout period. In Automatic Reset mode, the WDT monitors the RESET pin for incoming valid reset signals and will count down any inactive period before it forces a reset.

The MAX6796TPLD0+ is a low-power, high-precision reset supervisor designed to monitor and control power-on reset (POR) conditions. It provides a minimum reset voltage window detecting levels as low as 2.30V (100 mV below the current VDD threshold below which the device operates in low-power state). It supports reset signaling from the MAX6796 devices across multiple power supplies or supplies with varying voltages and has configurable logic that allows for both manual and automatic reset modes. It includes a Watchdog Timer (WDT) for safely restarting a system in the event that it becomes unresponsive and adjustable power-on reset (POR) time intervals so you can make sure the reset events are synchronized with the power signals. It also supports pulse frequency limiting and adjustable debounce circuits to ensure correct reset information is latched and reset signals are propagated even when the power is off. The MAX6796TPLD0+ is ideal for any application where detection of low voltage and fast reset signals is critical, such as in board-level reset controllers. It is available in both a small-footprint, 8-pin SOIC package and a 4-pin SOT-23 package for lower-power applications.

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