MAX9280GTN/V+WGG6

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Serializers and deserializers, or SerDes for short, are important components that enable digital transmission of high-speed serial interfaces. MAX9280GTN/V+WGG6 is a low-power, 28-Gbps dual-channel linear (de)serializer that supports a wide range of data rates up to 28 Gbps. This product is a combination of the MAX9280 deserializer and the MAX9282 serializer. In this article, we will discuss the application field and working principle of the MAX9280GTN/V+WGG6.

Application field

The MAX9280GTN/V+WGG6 is suitable for applications such as backplanes, optical networks, Ethernet, and consumer electronics that require high-speed serial data transmission. It can be used for a wide range of serial applications with data rates from 2 Gbps to 28 Gbps, such as dual-mode serial links, clock-and-data recovery (CDR) channels, forward error correction (FEC) blocks, or framers. It is available in a 38-ball WGG6 package.

The MAX9280GTN/V+WGG6 is designed to meet stringent eye mask requirements while minimizing jitter and power consumption. The product features 50% data-rate reduction mode to reduce the power consumption by 50%. The chip provides built-in phase-locked loops (PLLs) for clock and data recovery with fewer external components, and includes an FEC input/output for improved data transmission quality.

The MAX9280GTN/V+WGG6 also features a low-skew output clock buffer with 3.3-V LVDS swing. The chip\'s PLLs are sensitive to power supply noise and the chip can operate over a wide temperature range of -40 °C to 105 °C. It also has an integrated loopback feature for automatic self-test and calibration.

Working principle

The MAX9280GTN/V+WGG6 consists of two channels, a deserializer and a serializer. The deserializer takes high-speed serial data and converts it into a lower speed parallel data stream suitable for processing. The serializer takes low-speed parallel data and converts it into a high-speed serial data stream suitable for transmission.

The deserializer first extracts the clock (“CK”) signal from the serial data stream. The clock is the time reference used by the device to determine when to sample the data bits. The extracted clock is then used to re-sample the serial data stream into a parallel data stream. The output data is passes through a data quality check to ensure that the data is valid and is free from jitter and errors.

The serializer converts parallel input data into serial data with a data rate up to 28 Gbps. The serial data output is passed through a pre-emphasis driver to reduce data-dependent jitter and to improve the overall system performance. The output data is then passed through a low-pass filter to reduce the amount of high-frequency noise. The filtered data is converted into a 20-bit wide serial output data stream.

The MAX9280GTN/V+WGG6 also features an FEC input port, which can be used to increase the system data transmission rate by reducing the amount of errors in the transmitted data. The FEC data is used to detect and correct errors in the transmitted signal.

In addition, the product includes an integrated low-skew output clock buffer and a re-time buffer. The output clock buffer reduces the propagation delay of the signal that runs between the deserializer and the serializer, while the re-time buffer ensures that the jitter and skew of the clock are minimized. The re-time buffer also eliminates clock-data interleaving (CDI) artifacts.

The MAX9280GTN/V+WGG6 is designed to eliminate jitter and improve data transmission quality while meeting stringent parameters requirements. The product is suitable for a wide variety of applications and can be used to transmit data over long distances with low power consumption.

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