MSP430F423IPMR

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1. Describe

TI's MSP430™ family of ultra-low-power microcontrollers consists of multiple devices with different characteristics to form a peripheral set for various applications. This architecture, combines five low-power mode, optimized to extend battery life in portable measurement applications. equipment Features a powerful 16-bit RISC CPU, 16-bit registers and constant generators that help Maximum code efficiency. The Digitally Controlled Oscillator (DCO) allows the device to wake up from a low-power mode to an active mode in less than 6 µs. The MSP430F423IPMR series are microcontroller-configured ADCs with three independent 16-bit sigma-deltas, each with an integrated differential programmable gain amplifier input stage. Also includes a built-in 16-bit timer, 128-segment LCD drive capability, hardware multiplier and 14 I/O pins. Typical applications include high-resolution applications such as handheld metering devices, weighing scales, and energy meters.

2. Feature

    1. Low supply voltage range: 1.8 V to 3.6 V

    2. Ultra-low power consumption:

        – Active mode: 400 µA at 1 MHz, 3 V

        – Standby mode: 1.6 µA

        – Off mode (RAM reserved): 0.1 µA

    3. Five power saving modes

    4. Wake-up from standby in less than 6 µs

    5. Frequency Locked Loop, FLL+

    6. 16-bit RISC architecture, 125ns instruction cycle time

    7. Three independent 16-bit Sigma-Delta analog-to-digital converters (ADCs) with differential PGA inputs

    8. 16-bit Timer_A with three capture/compare registers

    9. Integrated LCD driver for 128 segments

  10. Serial communication interface (USART), asynchronous UART or synchronous SPI selectable by software

  11. Brownout detector

  12. Supply voltage supervisors and monitors with programmable level detection

  13. Serial on-board programming, no external programming voltage required, programmable code protection via safety fuses

  14. Bootloader (BSL)

  15. Family members include:

        – MSP430F423: 8KB + 256 B Flash, 256 B RAM

        – MSP430F425: 16KB + 256 B Flash, 512 B RAM

        – MSP430F427: 32KB + 256 B Flash, 1KB RAM

  16. Available in 64-pin Quad Flat Pack (LQFP)

3. Application

    1. Handheld metering equipment

    2. weighing scale

    3. Meter

4. Pin configuration

5. Operating mode

    1. Active Mode (AM)

        – All clocks are active.

    2. Low Power Mode 0 (LPM0)

        – The CPU is disabled.

        – ACLK and SMCLK remain active, MCLK is available to the module.

        – FLL+ loop control remains active.

    3. Low Power Mode 1 (LPM1)

        – The CPU is disabled.

        – ACLK and SMCLK remain active, MCLK is available to the module.

        – FLL+ loop control is disabled.

    4. Low Power Mode 2 (LPM2)

        – The CPU is disabled.

        – MCLK, FLL+ loop control and DCOCLK are disabled.

        – The DC generator of the DCO remains enabled.

        – ACLK remains active.

    5. Low Power Mode 3 (LPM3)

        – The CPU is disabled.

        – MCLK, FLL+ loop control and DCOCLK are disabled.

        – The DC generator of the DCO is disabled.

        – ACLK remains active.

    6. Low Power Mode 4 (LPM4)

        – The CPU is disabled.

        – ACLK is disabled.

        – MCLK, FLL+ loop control and DCOCLK are disabled.

        – The DC generator of the DCO is disabled.

        – The crystal oscillator is stopped.

6. CPU

The MSP430F423IPMR CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations other than program flow instructions perform seven addressing modes for source operands and four addressing modes for destination operands as register operations. The CPU integrates 16 registers to shorten the instruction execution time. The execution time for register-to-register operations is one cycle of the CPU clock. Four of these registers, R0 through R3, are dedicated to the program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general purpose registers. Peripherals connect to the CPU using data, address, and control buses. Peripherals can manage all commands.