MX25U6435FM2I-10G

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1. DESCRIPTION

MX25U6435FM2I-10G is 64Mb bits serial Flash memory, which is configured as 8,388,608 x 8 internally. When it is in two or four I/O mode, the structure becomes 33,554,432 bits x 2 or 16,777,216 bits x 4. MX25U6435FM2I-10G feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and Reset# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output. The MX25U6435FM2I-10G MXSMIO® (Serial Multi I/O) provides sequential read operation on whole chip. After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis for erase command is executed on sector (4K-byte), block (32K-byte), or block (64K-byte), or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. Advanced security features enhance the protection and security functions, please see security features section for more details. The MX25U6435FM2I-10G utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles.

2. GENERAL

    1. Supports Serial Peripheral Interface -- Mode 0 and Mode 3

    2. 67,108,864 x 1 bit structure or 33,554,432 x 2 bits (two I/O mode) structure or 16,777,216 x 4 bits (four I/O mode) structure

    3. Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each

        - Any Block can be erased individually

    4. Single Power Supply Operation

        - 1.65 to 2.0 volt for read, erase, and program operations

    5. Latch-up protected to 100mA from -1V to Vcc +1V

    6. Low Vcc write inhibit is from 1.0V to 1.4V

3. PERFORMANCE

    1. High Performance

        - Fast read for SPI mode

        - 1 I/O: 104MHz with 8 dummy cycles

        - 2 I/O: 84MHz with 4 dummy cycles, equivalent to 168MHz

        - 4 I/O: 104MHz with 2+4 dummy cycles, equivalent to 416MHz

        - Fast read for QPI mode

        - 4 I/O: 84MHz with 2+2 dummy cycles, equivalent to 336MHz

        - 4 I/O: 104MHz with 2+4 dummy cycles, equivalent to 416MHz

        - Fast program time: 0.5ms(typ.) and 3ms(max.)/page (256-byte per page)

        - Byte program time: 12us (typical)

        - 8/16/32/64 byte Wrap-Around Burst Read Mode

        - Fast erase time: 35ms (typ.)/sector (4K-byte per sector); 200ms(typ.)/block (32K-byte per block), 350ms(typ.) / block (64K-byte per block)

    2. Low Power Consumption

        - Low active read current: 20mA(typ.) at 104MHz, 15mA(typ.) at 84MHz

        - Low active erase current: 18mA (typ.) at Sector Erase, Block Erase (32KB/64KB); 20mA at Chip Erase

        - Low active programming current: 20mA (typ.)

        - Standby current: 15uA (typ.)

    3. Deep Power Down: 1.5uA(typ.)

    4. Typical 100,000 erase/program cycles

    5. 20 years data retention

4. SOFTWARE FEATURES

    1. Input Data Format

        - 1-byte Command code

    2. Advanced Security Features

        - Block lock protection

           The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions

        - Additional 4k-bit secured OTP for unique identifier

    3. Auto Erase and Auto Program Algorithm

        - Automatically erases and verifies data at selected sector or block

        - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths 

    4. Status Register Feature

    5. Command Reset

    6. Program/Erase Suspend

    7. Electronic Identification

        - JEDEC 1-byte manufacturer ID and 2-byte device ID

        - RES command for 1-byte Device ID

        - REMS command for 1-byte manufacturer ID and 1-byte device ID

    8. Support Serial Flash Discoverable Parameters (SFDP) mode

5. HARDWARE FEATURES

    1. SCLK Input

        - Serial clock input

    2. SI/SIO0

        - Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode

    3. SO/SIO1

        - Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode

    4. WP#/SIO2

        - Hardware write protection or serial data Input/Output for 4 x I/O read mode

    5. RESET#/SIO3

        - Hardware Reset pin or Serial input & Output for 4 x I/O read mode

    6. PACKAGE

        - 8-pin SOP (200mil)

        - 8-land WSON (6x5mm)

        -12-ball WLCSP (Ball Diameter 0.30mm)

        - All devices are RoHS Compliant and Halogen-free