PGA113AIDGSRG4

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1. Describe

PGA112 and PGA113AIDGSRG4 devices (binary and range gain) provides two analog inputs, a three-pin SPI interface, and software shutdown on a 10-pin VSSOP package. The PGA116 and PGA117 (binary and range gain) provide 10 analog inputs, a daisy-chain SPI interface, and hardware and software shutdown in a 20-pin TSSOP package. All versions offer internal calibration channel system level calibration. Channels must be GND, 0.9 VCAL, 0.1 VCAL, and VREF VCAL, connected to the external voltage of channel 0, used as a system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; range gains are: 1, 2, 5, 10, 20, 50, 100, and 200.

2. Feature

    1. Rail-to-rail input and output

    2. Offset: 25 μV (typ), 100 μV (max)

    3. Zero drift: 0.35 μV/°C (typ), 1.2 μV/°C (max)

    4. Low noise: 12 nV/√Hz

    5. Input offset current: ±5 nA max (25°C)

    6. Gain Error: 0.1% max (G ≤ 32), 0.3% max (G > 32)

    7. Binary gain: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112, PGA116)

    8. Range Gain: 1, 2, 5, 10, 20, 50, 100, 200 (PGA113, PGA117)

    9. Gain switching time: 200 ns

  10. 2-channel MUX: PGA112, PGA11310 Channel MUX: PGA116, PGA117

  11. Four internal calibration channels

  12. Amplifier optimized for driving CDAC ADCs

  13. Output swing: 50 mV to rail

  14. AVDD and DVDD for mixed voltage systems

  15. IQ = 1.1 mA (typ.)

  16. Software and hardware shutdown: IQ ≤ 4 μA (typ)

  17. Temperature range: –40°C to 125°C

  18. SPI™ interface (10 MHz) with daisy-chain capability

3. Application

    1. Remote electronic meter reading

    2. Automatic Gain Control

    3. Portable data collection

    4. PC-based signal acquisition system

    5. Test and Measurement

    6. programmable logic controller

    7. Battery powered instruments

    8. Handheld test equipment

4. Pin configuration

5. Pin Description

6. Application Information

The PGA113AIDGSRG4 family of devices are single-ended input, single-supply, programmable gain amplifiers (PGAs) with input multiplexers. Multiplexer channel selection and gain selection are done through a standard SPI interface. The PGA112 and PGA113AIDGSRG4 have a two-channel input MUX, and the PGA116 and PGA117 devices have a 10-channel input multiplexer. Binary Gain Selection for PGA112 and PGA116 Devices (1, 2, 4, 8, 16, 32, 64, 128) Oscilloscope Gain Selection for PGA113 and PGA117 Devices (1, 2, 5, 10, 20, 50, 100, 200) .All models use a split power architecture of analog power supply AVDD and digital power supply DVDD. This split-supply architecture allows easy connection of analog-to-digital converters (ADCs) and microcontrollers in systems with mixed supply voltages, such as 5 V for analog and 3 V for digital. Four internal calibration channels are provided for system level calibration. The channels are connected to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to VCAL/CH0, used as a system calibration reference. If VCAL is the system ADC reference, gain and offset calibration on the ADC can be easily accomplished with the PGA11x devices using only one MUX input. If calibration is not used, VCAL/CH0 can be used as a standard MUX input. All four versions provide a VREF pin that can be grounded, or extended to mid-supply, for single-supply systems that use mid-supply as a virtual ground. The PGA112 and PGA113 devices offer software-controlled shutdown for low standby power consumption. PGA116 and PGA117 The device provides hardware and software controlled shutdown for low standby power consumption. PGA112 and The PGA113 device has a 3-wire SPI digital interface; the PGA116 and PGA117 devices have a 4-wire SPI digital interface. The PGA116 and PGA117 devices also have daisy-chain capability.