| Allicdata Part #: | PI2EQX4401ZFE-ND |
| Manufacturer Part#: |
PI2EQX4401ZFE |
| Price: | $ 0.00 |
| Product Category: | Integrated Circuits (ICs) |
| Manufacturer: | Diodes Incorporated |
| Short Description: | IC REDRIVER PCIE 2CH 36TQFN |
| More Detail: | Buffer, ReDriver 2 Channel 2.5Gbps 36-TQFN-EP (6x5... |
| DataSheet: |  PI2EQX4401ZFE Datasheet/PDF |
| Quantity: | 1000 |
| 1 +: | 0.00000 |
Specifications
| Number of Channels: | 2 |
| Base Part Number: | PI2EQX4401 |
| Supplier Device Package: | 36-TQFN-EP (6x5) |
| Package / Case: | 36-WFQFN Exposed Pad |
| Operating Temperature: | 0°C ~ 70°C |
| Current - Supply: | -- |
| Voltage - Supply: | 1.7 V ~ 1.9 V |
| Signal Conditioning: | Input Equalization, Output De-Emphasis |
| Delay Time: | -- |
| Series: | -- |
| Data Rate (Max): | 2.5Gbps |
| Output: | CML |
| Input: | CML |
| Applications: | PCIe |
| Type: | Buffer, ReDriver |
| Part Status: | Obsolete |
| Packaging: | Tray |
Description
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PI2EQX4401ZFE is a compact high-speed level 4 (L4) electrical bus interface that features two independent, full-duplex transceivers, clock generation and loopback support. It is designed to bridge Asynchronous Transfer Mode (ATM) networks to interconnect LANs, WANs and metropolitan area networks (MANs).The PI2EQX4401ZFE combines two independent full-speed transceivers, a clock generator and loopback support, into a single package, offering a cost-effective alternative to costly discrete devices. With a low jitter phase-locked loop (PLL) and clock multiplication logic, the PI2EQX4401ZFE produces four independent, 125MHz clocks with additional skew minimization. The PI2EQX4401ZFE also supports user-selectable loopback for testing applications.The PI2EQX4401ZFE is optimized for use as an ATM bus interface for systems that require low-jitter clocks for high-speed applications. This device is particularly suitable for ATM LANs, MANs and WANs networks. The PI2EQX4401ZFE is also suitable for SONET, SDH and packet-based applications.The PI2EQX4401ZFE can be used as an interface between different networks. It can act as a buffer or repeater, or split the signal into two different channels. It is designed to transmit and receive multiple channels simultaneously, as well as to monitor, buffer and/or repeat signals across multiple clock domains. The PI2EQX4401ZFE also enables a user to multi-layer the signals to reduce protocol overhead and complexity.The PI2EQX4401ZFE is designed to work with many protocols, such as ATM, SONET, SDH and packet-based, as well as legacy networks, including Parallel Interconnect networks, RS-232 and more. The block diagram of the chip reveals the different clock domains and channels it supports. The inputs and outputs to the PI2EQX4401ZFE are formed of reference clocks and data signals. The incoming data is conditioned with multiple clock paths for local data manipulation and for asynchronously processing of different data rates. The device can be used in many types of topologies.In summary, the PI2EQX4401ZFE is a versatile electrical bus interface with two independent, full-duplex transceivers, clock generation and loopback support. It is designed to bridge Asynchronous Transfer Mode (ATM) networks to interconnect LANs, WANs and metropolitan area networks (MANs). It is suitable for many applications, such as buffering, repeating, or splitting signals across multiple clock domains. It is well suited for use in ATM, SONET, SDH and packet-based networks, in addition to a range of legacy networks.
The specific data is subject to PDF, and the above content is for reference
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