PIC24F08KL200-E/ST

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1. Describe

The PIC24F08KL200-E/ST family adds a full range of Economical, Low Pin Count and Low Power Devices Microchip's portfolio of 16-bit microcontrollers. aim in applications requiring low power consumption, but More computing power than 8-bit platforms available, these devices offer a range of tailored peripheral set, allowing designers to optimize simultaneously Price point and features are not sacrificed Features.

2. Peripheral functions

    1. All high current sink/source (18 mA/18 mA) input/output pins

    2. Configurable open-drain outputs on digital I/O pins

    3. Up to three external interrupt sources

    4. Two 16-bit timers/counters with selectable clocks source

    5. Up to two programmable 8-bit timers/counters prescaler

    6. Two Capture/Compare/PWM (CCP) modules

        - Modules automatically configure and drive I/O

        - Maximum 16-bit capture. Resolution 40 ns

        - 16 bits Compare with maximum value. Resolution 83.3 ns

        - 1-bit to 10-bit PWM resolution

    7. Up to one enhanced CCP module

        - Backward compatible with CCP

        - 1, 2 or 4 PWM outputs

        - Programmable dead time

        - Automatic shutdown on external events

    8. Up to two master synchronous serial port modules (MSSP) has two modes of operation

        - 3-wire SPI (all four modes)

        - I2C™ master, multi-master and slave modes and 7-bit/10-bit addressing

    9. Up to two UART modules

        - Supports RS-485, RS-232 and LIN/J2602

        - On-chip hardware encoder/decoder for IrDA®

        - Automatic wake-up from start bit

        - Automatic Baud Rate Detection (ABD)

        - Two-byte transmit and receive FIFO buffers

3. Special microcontroller features

    1. Operating voltage range from 1.8V to 3.6V

    2. 10,000 Erase/Write Cycle Endurance Flash Programs memory, typical

    3. 100,000 Erase/Write Cycle Endurance Data EEPROM, typical

    4. Flash and data EEPROM data retention

        - at least 40 years

    5. Self-programming under software control

    6. Programmable reference clock output

    7. Fail-Safe Clock Monitor (FSCM) operation

        - detect clock failure and switch to on-chip, Low Power RC (LPRC) Oscillator

    8. Power-on Reset (POR), Power-on Timer (PWRT) and Oscillator Start-up Timer (OST)

    9. Flexible Watchdog Timer (WDT)

        - Use own low power RC oscillator

        - Windowed operation mode

        - Programmable period from 2 ms to 131s

  10. In-Circuit Serial Programming™ (ICSP™) and In-Circuit Emulation (ICE) via 2 pins

  11. Programmable high/low voltage detection (HLVD)

  12. Programmable Brown-out Reset (BOR)

        - Configurable for software controlled operation and Shut down in sleep mode

        - Selectable trip points (1.8V, 2.7V and 3.0V)

        - Low power 2.0V POR rearm

4. Pin configuration

5. External oscillator pin

Many microcontrollers have at least two option oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator. The oscillator circuit should be placed on one side of the same board as the device. place oscillator Circuits close to corresponding oscillator pins with no circuit more than 0.5 inches (12 mm) between components and pins. The load capacitor should be placed next to the oscillator itself, on the same side board of directors. Use a ground copper pour around the oscillator circuit to isolate it from surrounding circuits. This ground copper pour should be routed directly to the microcontroller ground. Do not run traces of any signal traces or power ground pouring down. Also, if using a double-sided board, avoid leaving any traces on the other side of the board where the crystal will be placed. Queued packets can be handled with a single-sided layout to fully contain the oscillator pins. and fine pitch packages, it is not always possible to completely surround the pins and components. A suitable solution is to tie the damaged protection section to the mirror formation. In all cases, protection tracking must be back to the ground.

6. CPU

The PIC24F CPU has a 16-bit (data) modified Harvard with an enhanced instruction set and a 24-bit instruction word field with variable-length opcodes. The program counter (PC) is 23 bits wide and can handle up to 4M user program instructions memory space. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provide predictable execution. All instructions are executed in one cycle, except instructions that change program flow, move double word (MOV.D) instructions and table instructions. Overhead-free program loop constructs are supported using the interruptible REPEAT instruction at any time. PIC24F devices have 16 16-bit working registers in the programmer's model. Each working register can act as a data, address or address offset register. The 16th working register (W15) is used as Software Stack Pointer (SSP) for interrupts and calls. High 32 KB of data space memory map 16K word boundary EEPROM memory that can be optionally mapped to any program space program memory or data, defined by the 8-bit Program Space Visibility Page Address (PSVPAG) register. The program-to-data space mapping feature allows any instruction to access program space as if it were data space. The Instruction Set Architecture (ISA) is significantly enhanced over PIC18, but maintains an acceptable backward level of compatibility. All PIC18 instructions and addressing directly or through simple support modes macro. Many ISA enhancements have been driven by compiler efficiency requirements. The core supports Inherent (no operand), Relative, Literal, Memory Direct, and three sets of addressing modes. All modes support direct register and various register indirect modes. Each group provides up to seven addressing modes. Instructions and predefined addressing modes depend on their functional requirements. For most instructions, the core is capable of performing data (or program data) memory reads, working register (data) reads, data memory writes, and program (instruction) memory per instruction read cycle. As a result, three-argument instructions can be supported, allowing ternary operations (i.e. A+B=C) to execute in one cycle. High-speed, 17-bit by 17-bit multipliers include significantly enhanced core arithmetic power and throughput. Multiplier supports signed, unsigned and mixed mode, 16-bit by 16-bit or 8-bit by 8-bit integer multiplication. All multiply instructions are executed in one cycle. The 16-bit ALU has been enhanced with integer division assist to support iterative non-recovery hardware partitioning algorithms. It works with the REPEAT instruction loop mechanism and selects iterative divide instructions to support 32-bit (or 16 bits), divided by 16-bit signed and unsigned integer allocations. All division operations take 19 cycles to complete, but can be interrupted on any loop boundary. The PIC24F has a vectored exception scheme, with up to eight non-maskable trap sources and up to 118 interrupt sources. Each interrupt source can be assigned to one of seven priority levels.

7. High-performance CPU

    1. Modified Harvard architecture

    2. Up to 16 MIPS operation @ 32 MHz

    3. 8 MHz internal oscillator

        - 4x PLL options

        - Multiple division options

    4. 17-bit x 17-bit single-cycle hardware Decimal/Integer Multiplier

    5. 32-bit by 16-bit hardware divider

    6. 16 x 16-bit working register array

    7. C compiler optimized instruction set Architecture (ISA)

        - 76 basic instructions

        - Flexible addressing modes

    8. Linear program memory addressing

    9. Linear data memory addressing

  10. Two Address Generation Units (AGUs) for independent Read and write addressing of data memory

8. Power Management Mode

    1. Run - CPU, Flash, SRAM and peripherals on

    2. Doze - CPU clock runs slower than peripherals

    3. Idle - CPU off, SRAM and peripherals on

    4. Sleep - CPU, Flash and peripherals off, SRAM on

    5. Low power consumption

        - 150 µA/MHz run mode current, 1.8V typical

        - Idle mode current less than 80 µA/MHz at 1.8V

        - Sleep mode current as low as 30 nA at +25°C

        - Watchdog timer as low as 210 nA at +25°C

9. Simulation Features

    1. 10-bit, up to 12-channel analog-to-digital (A/D) converter

        - 500 ksps conversion rate

        - Transitions possible during sleep and idle

    2. Dual rail-to-rail analog comparators with Programmable input/output configuration 

    3. On-chip voltage reference