PIC24FJ128GA306-I/PT

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1. Extreme Low-Power Features

    1. Multiple Power Management Options for Extreme Power Reduction:

        - VBAT allows the device to transition to a backup battery for the lowest power consumption with RTCC

        - Deep Sleep allows near total power-down with the ability to wake-up on external triggers

        - Sleep and Idle modes selectively shut down peripherals and/or core for substantial power reduction and fast wake-up

        - Doze mode allows CPU to run at a lower clock speed than peripherals

    2. Alternate Clock modes Allow On-the-Fly Switching to a Lower Clock Speed for Selective Power Reduction

    3. Extreme Low-Power Current Consumption for Deep Sleep:

        - WDT: 270 nA @ 3.3V typical

        - RTCC: 400 nA @ 32 kHz, 3.3V typical

        - Deep Sleep current, 40 na, 3.3V typical

2. Peripheral Features

    1. LCD Display Controller:

        - Up to 60 segments by 8 commons

        - Internal charge pump and low-power, internal resistor biasing

        - Operation in Sleep mode

    2. Up to Five External Interrupt Sources

    3. Peripheral Pin Select (PPS): Allows Independent I/O Mapping of Many Peripherals

    4. Five 16-Bit Timers/Counters with Prescaler:

        - Can be paired as 32-bit timers/counters

    5. Six-Channel DMA supports All Peripheral modules:

        - Minimizes CPU overhead and increases data throughput

3. Peripheral Features (Continued)

    1. Seven Input Capture modules, each with a Dedicated 16-Bit Timer

    2. Seven Output Compare/PWM modules, each with a Dedicated 16-Bit Timer

    3. Enhanced Parallel Master/Slave Port (EPMP/EPSP)

    4. Hardware Real-Time Clock/Calendar (RTCC):

        - Runs in Deep Sleep and VBAT modes

    5. Two 3-Wire/4-Wire SPI modules (support 4 Frame modes) with 8-Level FIFO Buffer

    6. Two I2C™ modules Support Multi-Master/Slave mode and 7-Bit/10-Bit Addressing

    7. Four UART modules:

        - Support RS-485, RS-232 and LIN/J2602

        - On-chip hardware encoder/decoder for IrDA®

        - Auto-wake-up on Auto-Baud Detect

        - 4-level deep FIFO buffer

    8. Programmable 32-Bit Cyclic Redundancy Check (CRC) Generator

    9. Digital Signal Modulator Provides On-Chip FSK and PSK Modulation for a Digital Signal Stream

  10. Configurable Open-Drain Outputs on Digital I/O Pins

  11. High-Current Sink/Source (18 mA/18 mA) on All I/O Pins

4. Analog Features

    1. 10/12-Bit, 24-Channel Analog-to-Digital (A/D) Converter:

        - Conversion rate of 500 ksps (10-bit), 200 ksps (12-bit)

        - Conversion available during Sleep and Idle

    2. Three Rail-to-Rail Enhanced Analog Comparators with Programmable Input/Output Configuration

    3. On-Chip Programmable Voltage Reference

    4. Charge Time Measurement Unit (CTMU):

        - Used for capacitive touch sensing, up to 24 channels

        - Time measurement down to 1 ns resolution

        - CTMU temperature sensing

5. High-Performance CPU

    1. Modified Harvard Architecture

    2. Up to 16 MIPS Operation @ 32 MHz

    3. 8 MHz Internal Oscillator:

        - 4x PLL option

        - Multiple clock divide options

        - Fast start-up

    4. 17-Bit x 17-Bit Single-Cycle Hardware Fractional/Integer Multiplier

    5. 32-Bit by 16-Bit Hardware Divider

    6. 16 x 16-Bit Working Register Array

    7. C Compiler Optimized Instruction Set Architecture

    8. Two Address Generation Units for Separate Read and Write Addressing of Data Memory

6. Special Microcontroller Features

    1. Operating Voltage Range of 2.0V to 3.6V

    2. Two On-Chip Voltage Regulators (1.8V and 1.2V) for Regular and Extreme Low-Power Operation

    3. 20,000 Erase/Write Cycle Endurance Flash Program Memory, Typical

    4. Flash Data Retention: 20 Years Minimum

    5. Self-Programmable under Software Control

    6. Programmable Reference Clock Output

    7. In-Circuit Serial Programming™ (ICSP™) and In-Circuit Emulation (ICE) via 2 Pins

    8. JTAG Boundary Scan Support

    9. Fail-Safe Clock Monitor Operation:

        - Detects clock failure and switches to on-chip, low-power RC oscillator

  10. Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

  11. Brown-out Reset (BOR) with Operation Below VBOR

  12. High/Low-Voltage Detect (HLVD)

  13. Flexible Watchdog Timer (WDT) with its Own RC Oscillator for Reliable Operation

  14. Standard and Ultra Low-Power Watchdog Timers (ULPW) for Reliable Operation in Standard and Deep Sleep modes