PIC24FJ16GA002-I/SO

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1. Special Microcontroller Features

    1. Operating Voltage Range of 2.0V to 3.6V

    2. 5.5V Tolerant Input (digital pins only)

    3. High-Current Sink/Source (18 mA/18 mA) on All I/O Pins

    4. Flash Program Memory:

        - 10,000 erase/write

        - 20-year data retention minimum

    5. Power Management modes:

        - Sleep, Idle, Doze and Alternate Clock modes

        - Operating current: 650 A/MIPS, typical at 2.0V

        - Sleep current: 150 nA, typical at 2.0V

    6. Fail-Safe Clock Monitor (FSCM) Operation:

        - Detects clock failure and switches to on-chip, low-power RC oscillator

    7. On-Chip, 2.5V Regulator with Tracking mode

    8. Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

    9. Flexible Watchdog Timer (WDT) with On-Chip, Low-Power RC Oscillator for Reliable Operation

  10. In-Circuit Serial Programming™ (ICSP™) and In-Circuit Debug (ICD) via 2 Pins

  11. JTAG Boundary Scan Support

2. Peripheral Features

    1. Peripheral Pin Select (PPS):

        - Allows independent I/O mapping of many peripherals

        - Up to 26 available pins (44-pin devices)

        - Continuous hardware integrity checking and safety interlocks prevent unintentional configuration changes

    2. 8-Bit Parallel Master/Slave Port (PMP/PSP):

        - Up to 16-bit multiplexed addressing, with up to 11 dedicated address pins on 44-pin devices

        - Programmable polarity on control lines

    3. Hardware Real-Time Clock/Calendar (RTCC):

        - Provides clock, calendar and alarm functions

    4. Programmable Cyclic Redundancy Check (CRC)

    5. Two 3-Wire/4-Wire SPI modules (support 4 Frame modes) with 8-Level FIFO Buffer

    6. Two I2C™ modules Support Multi-Master/Slave mode and 7-Bit/10-Bit Addressing

    7. Two UART modules:

        - Supports RS-485, RS-232, and LIN/J2602

        - On-chip hardware encoder/decoder for IrDA®

        - Auto-wake-up on Start bit

        - Auto-Baud Detect

        - 4-level deep FIFO buffer

    8. Five 16-Bit Timers/Counters with Programmable Prescaler

    9. Five 16-Bit Capture Inputs

  10. Five 16-Bit Compare/PWM Outputs

  11. Configurable Open-Drain Outputs on Digital I/O Pins

  12. Up to 3 External Interrupt Sources

3. High-Performance CPU

    1. Modified Harvard Architecture

    2. Up to 16 MIPS Operation @ 32 MHz

    3. 8 MHz Internal Oscillator with 4x PLL Option and Multiple Divide Options

    4. 17-Bit by 17-Bit Single-Cycle Hardware Multiplier

    5. 32-Bit by 16-Bit Hardware Divider

    6. 16-Bit x 16-Bit Working Register Array

    7. C Compiler Optimized Instruction Set Architecture:

        - 76 base instructions

        - Flexible addressing modes

    8. Two Address Generation Units (AGUs) for Separate Read and Write Addressing of Data Memory

4. Analog Features

    1. 10-Bit, up to 13-Channel Analog-to-Digital Converter:

        - 500 ksps conversion rate

        - Conversion available during Sleep and Idle

    2. Dual Analog Comparators with Programmable Input/Output Configuration

5. Other Special Features

    1. Communications: 

        The PIC24FJ64GA004 family incorporates a range of serial communication peripherals to handle a range of application requirements. There are two independent I2C modules that support both Master and Slave modes of operation. Devices also have, through the Peripheral Pin Select (PPS) feature, two independent UARTs with built-in IrDA encoder/decoders and two SPI modules.

    2. Peripheral Pin Select (PPS): 

        The Peripheral Pin Select feature allows most digital peripherals to be mapped over a fixed set of digital I/O pins. Users may independently map the input and/or output of any one of the many digital peripherals to any one of the I/O pins.

    3. Parallel Master/Enhanced Parallel Slave Port: 

        One of the general purpose I/O ports can be reconfigured for enhanced parallel data communications. In this mode, the port can be configured for both master and slave operations, and supports 8-bit and 16-bit data transfers with up to 16 external address lines in Master modes.

    4. Real-Time Clock/Calendar (RTCC): 

         This module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application.

    5. 10-Bit A/D Converter: 

         This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, as well as faster sampling speeds.