PIC24FV32KA302-I/SO

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1. Functions

    1. Wide operating voltage range:

        - 1.8V to 3.6V (PIC24F devices)

        - 2.0V to 5.5V (PIC24FV devices)

    2. Low-power wake-up sources and monitors:

        - Ultra Low Power Wakeup (ULPWU) for sleep/deep sleep

        - Low power watchdog timer (DSWDT) for deep sleep

        - Very low power Brown-out Reset (DSBOR) for deep sleep, LPBOR for all other modes

    3. System frequency range declaration bits:

        - Declared frequency range to optimize current consumption.

    4. On-chip standard Watchdog Timer (WDT)

        - Low-power RC oscillator for reliable operation

    5. Programmable high/low voltage detection (HLVD)

    6. Standard Brown-out Reset (BOR) with 3 programmable trip points that can be disabled during sleep

    7. High current sink/source (18 mA/18 mA) on all I/O pins

    8. Flash program memory

        - Erase/Write cycles: at least 10,000

        - Data retention of at least 40 years

    9. Data EEPROM:

        - Erase/Write Cycles: 100,000 minimum

        - Data retention of at least 40 years

  10. Fail-Safe Clock Monitor (FSCM)

  11. Programmable reference clock output

  12. Self-programming under software control

  13. In-Circuit Serial Programming™ (ICSP™) and In-Circuit Debug (ICD) via 2 pins

2. Peripheral function

    1. Hardware Real Time Clock and Calendar (RTCC):

        - Provides clock, calendar and alarm functions

        - Can run in deep sleep mode

        - Can use 50/60 Hz power line input as clock source

    2. Programmable 32-bit Cyclic Redundancy Check (CRC)

    3. Multiple serial communication modules:

        - Two 3/4 wire SPI modules

        - Two I2C modules supporting multi-master/slave

        - Two UART modules supporting RS-485, RS-232, LIN/J2602, IrDA®

    4. Five 16-bit timers/counters with programmable prescalers:

        - Can be paired as 32-bit timer/counter

    5. Three 16-bit capture inputs with dedicated timers

    6. Three 16-bit compare/PWM outputs with dedicated timers

    7. Configurable open-drain outputs on digital I/O pins

    8. Up to three external interrupt sources

3. Simulation function

    1. 12-bit, up to 16-channel analog-to-digital converter:

        - 100 ksps conversion rate

        - Transitions possible during sleep and idle

        - Auto-sampling, timer-based options for sleep and idle modes

        - Wake up auto compare option

    2. Dual rail-to-rail analog comparator with programmable input/output configuration

    3. On-chip voltage reference

    4. Internal temperature sensor

    5. Charge Time Measurement Unit (CTMU):

        - For capacitive sensing, 16 channels

        - Time measurement with resolution down to 200 ps

        - Delay/pulse generation with resolution down to 1 ns

4. power management mode

    1. Run - CPU, Flash, SRAM and peripherals on

    2. Doze - CPU clock runs slower than peripherals

    3. Idle - CPU off, Flash, SRAM and peripherals on

    4. Sleep - CPU, Flash and peripherals off, SRAM on

    5. Deep sleep - CPU, Flash, SRAM and most peripherals are turned off;

        - Multiple autonomous wake-up sources

    6. Low power consumption:

        - Run mode current as low as 8 μA, typical

        - Idle mode current as low as 2.2 μA, typical

        - Deep-sleep mode current as low as 20 nA, typical

        - Real time clock/calendar current down to 700 nA, 32 kHz, 1.8V

        - Watchdog timer is 500 nA, 1.8V typical

5. High performance CPU

    1. Modified Harvard architecture

    2. Up to 16 MIPS operation @ 32 MHz

    3. 8 MHz internal oscillator

        - Has 4x PLL options and multiple divide options

    4. 17-bit x 17-bit single-cycle hardware multiplier

    5. 32-bit by 16-bit hardware divider,

        - 16-bit x 16-bit working register array

    6. C compiler optimized instruction set architecture

6. CPU

PIC24F CPUs have an improved 16-bit (data) Harvard with an enhanced instruction set and 24-bit instruction word field with variable length opcodes. The program counter (PC) is 23 bits wide and can handle up to 4M of user program instruction memory. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provide predictable execution. All instructions are executed in one cycle, except for instructions that change program flow, move double word (MOV.D) instructions, and table instructions. Overhead-free program loop constructs are supported at any time using interruptible REPEAT instructions. PIC24F devices have 16 16-bit working registers in the programmer model. Each working register can act as a data, address or address offset register. The 16th working register (W15) is used as the software stack pointer (SSP) for interrupts and calls. The upper 32 KB of the data space memory map can optionally be mapped to any program space program memory or 16K word boundary EEPROM memory for data, defined by the 8-bit Program Space Visibility Page Address (PSVPAG) register. This program-to-data space mapping feature allows any instruction to access program space as if it were data space. The Instruction Set Architecture (ISA) has been significantly enhanced compared to the PIC18, but maintains an acceptable level of backward compatibility. All PIC18 instructions and addressing modes are supported directly or via simple macros. Many ISA enhancements are done through compilation er efficiency needs. The core supports Inherent (no operand), Relative, Literal, Memory Direct, and three sets of addressing modes. All modes support direct register and various register indirect modes. Each group provides up to seven addressing modes. Instructions and predefined addressing modes depend on their functional requirements. For most instructions, the core is capable of performing data (or program data) memory reads, reading registers (data), writing to data memory, and reading program (instruction) memory per instruction cycle of work. As a result, the three-argument directive can be Yes, allowing ternary operations (i.e. A + B = C) to be executed in one cycle. High speed, 17-bit by 17-bit multipliers include significantly enhanced core arithmetic power and throughput. Signed, unsigned and mixed modes, 16-bit x 16-bit or 8-bit by 8-bit integer multiplication. All multiply instructions are executed in one cycle. The 16-bit ALU has been enhanced with integer division assist to support iterative non-recovery hardware partitioning algorithms. It works with the REPEAT instruction loop mechanism and selects iterative divide instructions to support 32-bit (or 16-bit) divide by 16-bit signed and unsigned integer allocations. All division operations take 19 cycles to complete, but can be interrupted on any cycle boundary. The PIC24F has a vectored exception scheme for up to eight non-maskable trap sources and up to 118 interrupt sources. Each interrupt source can be assigned to one of seven priority levels.