PIC32MX575F512L-80I/BG

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1. Feature

    1. 5-stage pipeline

    2. 32-bit address and datapath

    3. MIPS32 Enhanced Architecture (Release 2)

        - Multiply Add and Multiply Subtract instruct

        - Targeted multiplication instructions

        - Zero/One detection command

        - wait for instructions

        - Conditional move instructions (MOVN, MOVZ)

        - Vector interrupt

        - Programmable exception vector library

        - Atomic interrupt enable/disable

        - GPR shadow registers to minimize latency for interrupt handler

        - Bit field manipulation instructions

    4. MIPS16e® code compression

        - 16-bit encoding of 32-bit instructions Improve code density

        - Special PC-related instructions for efficient use Load addresses and constants

        - Save and restore macros Set up and tear down stack frames within a subroutine

        - Improved support for handling 8-bit and 16-bit type of data

    5. Simple Fixed Mapping Transformation (FMT) mechanism

    6. Simple dual bus interface

        - Separate 32-bit address and data buses

        - Transactions can be aborted to improve interrupt latency

    7. Autonomous multiply/divide unit

        - Maximum issue rate for a 32x16 multiplication per clock

        - Maximum issue rate for a 32x32 multiplication every other clock

        - Early iterative division. be at least 11 years old and up to 33 clock delays 

        - Minimum frequency: 0 MHz

        - Low power mode (triggered by WAIT Instructions)

        - Extensive use of local gated clocks

    8. EJTAG debug and instruction trace

        - Support single step

        - virtual instruction and data addresses/values

        - breakpoint

        - PC trace with trace compression

2. Core module

    1. Execution unit

    2. Multiplication/Division Unit (MDU)

    3. System Control Coprocessor (CP0)

    4. Fixed Mapping Transformation (FMT)

    5. Dual internal bus interfaces

    6. Energy management

    7. MIPS16e® support

    8. Enhanced JTAG (EJTAG) controller

3. The USB module includes the following features

    1. USB Full-speed support for host and device

    2. Low-speed host support

    3. USB OTG support

    4. Integrated signaling resistors

    5. Integrated analog comparators for VBUS monitoring

    6. Integrated USB transceiver

    7. Transaction handshaking performed by hardware

    8. Endpoint buffering anywhere in system RAM

    9. Integrated DMA to access system RAM and Flash

4. The Interrupt Controller module includes the following features

    1. Up to 96 interrupt sources

    2. Up to 64 interrupt vectors

    3. Single and multi-vector mode operations

    4. Five external interrupts with edge polarity control

    5. Interrupt proximity timer

    6. Seven user-selectable priority levels for each vector

    7. Four user-selectable sub-priority levels within each priority

    8. Dedicated shadow set for user-selectable priority level

    9. Software can generate any interrupt

  10. User-configurable interrupt vector table location

  11. User-configurable interrupt vector spacing

5. The Oscillator module has the following features

    1. A total of four external and internal oscillator options as clock sources

    2. On-chip PLL with user-selectable input divider, multiplier and output divider to boost operating frequency on select internal and external oscillator sources

    3. On-chip user-selectable divisor postscaler on select oscillator sources

    4. Software-controllable switching between various clock sources

    5. A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown

    6. Dedicated On-Chip PLL for USB peripheral

6. Following are some of the key features of the DMA controller module

    1. Four identical channels, each featuring:

        - Auto-increment source and destination address registers

        - Source and destination pointers

        - Memory to memory and memory to peripheral transfers

    2. Automatic word-size detection:

        - Transfer granularity, down to byte level

        - Bytes need not be word-aligned at source and destination

    3. Fixed priority channel arbitration

    4. Flexible DMA channel operating modes:

        - Manual (software) or automatic (interrupt) DMA requests

        - One-Shot or Auto-Repeat Block Transfer modes

        - Channel-to-channel chaining

    5. Flexible DMA requests:

        - A DMA request can be selected from any of the peripheral interrupt sources

        - Each channel can select any (appropriate) observable interrupt as its DMA request source

        - A DMA transfer abort can be selected from any of the peripheral interrupt sources

        - Pattern (data) match transfer termination

    6. Multiple DMA channel status interrupts:

        - DMA channel block transfer complete

        - Source empty or half empty

        - Destination full or half full

        - DMA transfer aborted due to an external event

        - Invalid DMA address generated

    7. DMA debug support features:

        - Most recent address accessed by a DMA channel

        - Most recent DMA channel to transfer data

    8. CRC Generation module:

        - CRC module can be assigned to any of the available channels

        - CRC module is highly configurable