Allicdata Part #: | 576-4381-2-ND |
Manufacturer Part#: |
PL560-47QC-R |
Price: | $ 5.26 |
Product Category: | Integrated Circuits (ICs) |
Manufacturer: | Microchip Technology |
Short Description: | IC VCXO AFM 2X MULTIPLIER CLOCK |
More Detail: | N/A |
DataSheet: | PL560-47QC-R Datasheet/PDF |
Quantity: | 1000 |
3000 +: | $ 4.78891 |
Differential - Input:Output: | No/No |
Base Part Number: | PL560 |
Supplier Device Package: | 16-QFN (3x3) |
Package / Case: | 16-WFQFN Exposed Pad |
Mounting Type: | Surface Mount |
Operating Temperature: | 0°C ~ 70°C |
Voltage - Supply: | 2.97 V ~ 3.63 V |
Divider/Multiplier: | No/Yes |
Frequency - Max: | 160MHz |
Series: | -- |
Ratio - Input:Output: | 1:1 |
Number of Circuits: | 1 |
Output: | LVCMOS, LVTTL |
Input: | Crystal |
PLL: | No |
Part Status: | Active |
Packaging: | Tape & Reel (TR) |
Due to market price fluctuations, if you need to purchase or consult the price. You can contact us or emial to us: sales@allicdata.com
The PL560-47QC-R is a high frequency clock generator, phase-locked loop (PLL), frequency synthesizer module which integrates a wide range of features into a single, cost-efficient package. As an all-in-one clock generation and digital frequency synthesizer, PL560-47QC-R provides customers with maximum flexibility in the design of their custom equipment.
Application Field
The PL560-47QC-R is ideal for advanced packet processing applications, such as 4G/LTE, WiMAX, LTE-A, 5G mobile networks, storage, high-end networking, and related high frequency applications. With a wide frequency range of 93.75 to 622.08 MHz, the PL560-47QC-R supports various types of signals, including but not limited to DDR3, DDR4, SDR/DDR, SONET/SDH, Ethernet, radio, FPGA/ASIC, and VoIP. Additionally, the PL560-47QC-R can be used in a wide range of devices, including PCs, servers, routers, switches, DPSs, EDFA, FPGA/ASICs, wireless modems, VoIP phones, and other digital equipments.
Working Principle
The PL560-47QC-R utilizes a phase-locked loop (PLL) architecture consisting of four primary components--a phase detector, a low-pass filter (LPF), an oscillator, and a frequency divider/phase shifter. The phase detector continually compares the input reference frequency to the feedback frequency, and outputs a difference signal to the LPF. The LPF then filters out the high-frequency noise generated by the phase detector, and passes the error signal to the oscillator. The oscillator then adjusts its output frequency to reduce the error signal to zero. Finally, the frequency divider/phase shifter adjusts the frequency and phase of the output signal accordingly.
The PL560-47QC-R can be programmed to perform a wide range of operations, including multiplication, division, prescaler, frequency and phase adjustment, and jitter reduction. The output of the PLL can be adjusted by changing the feedback divider setting. For example, if the feedback divider is set to 1, the output frequency will be equal to the input reference frequency. Similarly, if the feedback divider is set to 2, the output frequency will be equal to half of the input reference frequency.
The PL560-47QC-R also supports many different types of modulation, including Pulse Width Modulation (PWM), Frequency Modulation (FM), and Phase Modulation (PM). The modulation depth and type can be adjusted to provide better dynamic performance and minimize jitter. Additionally, the PL560-47QC-R can also be used to synthesize non-integer frequencies.
In summary, the PL560-47QC-R is an advanced and cost-efficient clock generation and digital frequency synthesizer module. It supports a wide range of modulation types and provides customers with maximum flexibility in the design of their custom equipment. The PL560-47QC-R is ideal for packet processing and high frequency applications, including but not limited to 4G/LTE, WiMAX, and 5G mobile networks.
The specific data is subject to PDF, and the above content is for reference
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