SGTL5000XNLA3R2 Integrated Circuits (ICs) |
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Allicdata Part #: | 568-13255-2-ND |
Manufacturer Part#: |
SGTL5000XNLA3R2 |
Price: | $ 0.00 |
Product Category: | Integrated Circuits (ICs) |
Manufacturer: | NXP USA Inc |
Short Description: | IC AUDIO CODEC STEREO 20-QFNStereo Audio Interface... |
More Detail: | N/A |
DataSheet: | SGTL5000XNLA3R2 Datasheet/PDF |
Quantity: | 25000 |
Series: | SGTL5000 |
Packaging: | Tape & Reel (TR) |
Part Status: | Active |
Type: | Stereo Audio |
Data Interface: | I²C, Serial, SPI™ |
Resolution (Bits): | -- |
Number of ADCs / DACs: | 1 / 1 |
Sigma Delta: | No |
S/N Ratio, ADCs / DACs (db) Typ: | 90 / 100 |
Dynamic Range, ADCs / DACs (db) Typ: | -- |
Voltage - Supply, Analog: | 1.62 V ~ 3.6 V |
Voltage - Supply, Digital: | 1.1 V ~ 2 V, 1.62 V ~ 3.6 V |
Operating Temperature: | -40°C ~ 85°C |
Mounting Type: | Surface Mount |
Package / Case: | 20-UFQFN Exposed Pad |
Supplier Device Package: | 20-QFN-EP (3x3) |
Base Part Number: | SGTL5000 |
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1. Describe
SGTL5000XNLA3R2 is a low power stereo codec with headphone amplifier Complete Audio Solutions from NXP Requires LINEIN, MIC_IN, LINEOUT, headphone out and Digital input/output. Derived from best-in-class architecture, NXP integrated products currently on the market. SGTL5000 can Ultra-low power consumption with very high performance and functionality, All in one of the smallest footprints available. Target markets include Media Players, Navigation Devices, Smartphones, Tablets, Medical equipment, sports equipment, consumer audio equipment, etc. Features such as the capless headphone design and internal PLL help Reduce overall system cost.
2. Feature
1. Analog input
- Stereo LINEIN - supports external analog input
- Stereo LINEIN - Low Power Codec Bypass
- Provides MIC bias
- Programmable MIC gain
- ADC - 85 dB SNR (-60 dB input) and -73 dB THD+N (VDDA = 1.8 V)
2. Analog output
- HP output - no cover design
- HP output - 62.5 mW max, 1.02 kHz sine wave, 16 Ω load, 3.3 V
- HP output - 100 dB SNR (-60 dB input) and -80 dB THD+N (VDDA = 1.8 V, 16 Ω load, DAC to headphone)
- LINEOUT - 100 dB SNR (-60 dB input) and -85 dB THD+N (VDDIO = 3.3V)
3. Digital input/output
- I2S port allows routing to application processor
4. Integrated digital processing
- NXP Surround, NXP Bass, Tone Control/Parametric EQ/Graphic Equalizer Clock/Control
- PLL allows input of 8.0 MHz to 27 MHz system clock - standard Audio clock from PLL
5. Power
- Designed to operate from 1.62 to 3.6 volts
3. Pin configuration
4. Function Description
The SGTL5000 is a low-power stereo codec with Integrated headphone amplifier. It aims to provide a A complete audio solution for portable products that need it LINEIN, microphone input, LINEOUT, headphone output and digital I/O. Its architecture is derived from best-in-class NXP integration Products currently on the market, SGTL5000 is Ultra-low power consumption, high performance and functionality, all in one of the smallest footprints usable. Target markets include portable media players, GPS units and smartphones. Unlimited etc. Headphone Design and USB Clock Mode (12 MHz SYS_MCLK input) helps reduce overall system cost.
1. The SGTL5000 accepts the following inputs
- Line in
- Microphone input with microphone bias
- Digital I2S input
2. SGTL5000 supports the following outputs:
- Line out
- Headphone output
- Digital I2S output
3. Digital audio processing for product differentiation
- Digital mixer
- NXP Surround Sound
- NXP Bass Boost
- Tone Control, Parametric EQ or Graphic EQ
SGTL5000 can accept external standard master clock with multiples of sampling frequency. Additionally, it can take non-standard frequencies and use the internal PLL to export audio clock. The device supports sampling frequencies of 8.0 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 96 kHz.
5. Typical application
For new designs, and 20 QFN or 32 QFN section, the external VDDD power supply connection is Requires a capacitor connection from VDDD to 0.1 μF ground.
1. CPFILT: The CPFILT capacitor value is 0.1 μF. If both VDDIO and VDDA ≤ 3.0 V, the CPFILT pin must be connected to a 0.1 μF capacitor to GND. If either is > 3.0 V, the CPFILT cover must not be placed.
2. HP_VGND: Do not connect HP_VGND to system ground, even if not used. This is a virtual ground (DC voltage) and should not be connected to an actual "0 volt ground". Use the widest and shortest possible trace to HP_VGND.
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