SN65LVDS050DR

SN65LVDS050DR is a low-voltage differential line driver designed for data communication with data rates of up to 200 megabits per second. It supports the low-voltage differential signaling (LVDS) standard. This LVDS driver provides differential line terminating resistors on its receiver inputs as well as differential line driving capability on its outputs. It is commonly used in high-speed digital data communications links, such as Gigabit Ethernet, automotive technologies and radio communication.

The LVDS driver can configured in multiple modes such as single ended, dual line and multiple (quasi-differential) modes by changing the combination of external resistors. Its internal biasing circuit also provides additional configuration schemes allowing the user to choose the levels of positive and negative slew rates to balance the differential drive current. This chip is also capable of providing more than 20dB of output common mode rejection at the receiver end of a link and also provides a low impedance source and sink for the LVDS signaling.

The SN65LVDS050DR application field can include any applications that require LVDS (Low Voltage Differential Signaling) communications at speeds up to 200 Mbps, such as GigE vision, medical imaging, consumer interface, data storage and embedded interconnect. The SN65LVDS050DR can also be used in automotive and industrial applications, such as data links, medical I/O, or point-to-point communication for low-voltage systems. This device is broadly used in high-speed serial data communications applications, such as backplane and board-to-board links.

The SN65LVDS050DR works on a voltage common mode of 2.0V, the system which is to be connected with the SN65LVDS050DR should have the common mode voltage levels of 1.2V and 3.3V. The pin 1 and 3 of the driver are connected respectively to the supply Vin- and Vin+ . Pin 2,4 and 5 are left unconnected. After the driver configuration is done, Pin 6,7,9 and 11 are connected to the LVDs receiver board to provide the bi-directional transmission of data.

Pin 8, 10 and 12 are connected to the ground. The common mode voltage at the transmitter is set to 1.5V. Pins 6 and 7 implement the differential output, with 6 acting as non-inverting output and 7 being the inverting output. SN65LVDS050DR can source and sink current of equal magnitude up to 24mA, depending on external biasing conditions. SN65LVDS050DR contains four independent receivers which form a self-clocking logic system providing data recovery and differential termination.

The LVDS receiver works in the multistandard compatible with the LVTTL and HSSTL logic families. The SN65LVDS050DR allows for greater data rate transmissions over a shorter distance compared with traditional transformer based systems. The receiver inputs offer a differential input with a 100Ω termination resistance. This termination resistance is set to give optimum performance for the receiver\'s midpoint voltage and transition time. The transition time of the receiver input is 750ps max.

In conclusion, the SN65LVDS050DR provides a high-speed digital communication link used in a variety of applications due to its low power consumption and small footprint. Its internal biasing circuit can provide different levels of positive and negative slew rates and improved output common-mode rejection. The device is used to send and receive data up to 200Mbps and is also compatible with LVTTL and HSSTL logic families. The receiver input impedance matches with a 100Ω termination resistance which provides optimal performance.