SN65MLVD2DRBR

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1. DESCRIPTION

The SN65MLVD2DRBR are single-channel M-LVDS receivers. These devices are designed in full compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at signaling rates up to 250 Mbps. Each receiver channel is controlled by a receive enable (RE). When RE = low, the corresponding channel is enabled; when RE = high, the corresponding channel is disabled. The M-LVDS standard defines two types of receivers, designated as Type-1 and Type-2. Type-1 receivers have thresholds centered about zero with 25 mV of hysteresis to prevent output oscillations with loss of input; Type-2 receivers implement a failsafe by using an offset threshold. Receiver outputs are slew rate controlled to reduce EMI and crosstalk effects associated with large current surges. The devices are characterized for operation from –40°C to 85°C.

2. FEATURES

    1. Low-Voltage Differential 30-Ω to 55-Ω Line Receivers for Signaling Rates(1) up to 250Mbps; Clock Frequencies up to 125MHz

    2. SN65MLVD2 Type-1 Receiver Incorporates 25 mV of Input Threshold Hysteresis

    3. SN65MLVD3 Type-2 Receiver Provides 100 mV Offset Threshold to Detect Open-Circuit and Idle-Bus Conditions

    4. Wide Receiver Input Common-Mode Voltage Range, –1 V to 3.4 V, Allows 2 V of Ground Noise

    5. Improved VIT (35 mV)

    6. Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Topology

    7. High Input Impedance with Low Supply Voltage

    8. Bus-Pin HBM ESD Protection Exceeds 9 kV

    9. Packaged in 8-Pin SON (DRB) 70% Smaller Than 8-Pin SOIC

3. APPLICATIONS

    1. Parallel Multipoint Data and Clock  

        - Transmission via Backplanes and Cables

    2. Cellular Base Stations

    3. Central Office Switches

    4. Network Switches and Routers