SN74LV573ADBR Integrated Circuits (ICs) |
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| Allicdata Part #: | 296-3839-2-ND |
| Manufacturer Part#: |
SN74LV573ADBR |
| Price: | $ 0.12 |
| Product Category: | Integrated Circuits (ICs) |
| Manufacturer: | Texas Instruments |
| Short Description: | IC OCT D LATCH TRI-ST 20-SSOP |
| More Detail: | D-Type Transparent Latch 1 Channel 8:8 IC Tri-Stat... |
| DataSheet: | SN74LV573ADBR Datasheet/PDF |
| Quantity: | 1000 |
| 2000 +: | $ 0.10546 |
| 6000 +: | $ 0.09866 |
| 10000 +: | $ 0.09185 |
| Series: | 74LV |
| Packaging: | Tape & Reel (TR) |
| Part Status: | Active |
| Logic Type: | D-Type Transparent Latch |
| Circuit: | 8:8 |
| Output Type: | Tri-State |
| Voltage - Supply: | 2 V ~ 5.5 V |
| Independent Circuits: | 1 |
| Delay Time - Propagation: | 1ns |
| Current - Output High, Low: | 16mA, 16mA |
| Operating Temperature: | -40°C ~ 85°C |
| Mounting Type: | Surface Mount |
| Package / Case: | 20-SSOP (0.209", 5.30mm Width) |
| Supplier Device Package: | 20-SSOP |
| Base Part Number: | 74LV573 |
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The SN74LV573ADBR is a type of logic device categorized as latches. It is a Dual/Quad device that is 5V tolerant, with 7ns propagation delay. As its name implies, it is a 5V logic device. This logic device acts as a latch; it is used to store data inputted into it until the data is reset when the clock signal goes low.
The SN74LV573ADBR has 16 pins, with two 8-pin packages. Its pins are labeled J, K, C (clock), D (data), G (ground/Vss), W (power/vcc), and four R/S pins (reset/set). The inputs for the device are J, K, C, D, and R/S. The outputs of the device are Q and Q- bar.
The device has three operation modes: Set/Reset, D-Latch, and Edge-Triggered D Flip-Flop. In Set/Reset mode, navigation of the logic state is based on signals given at the R/S pins. A set signal is activated when R is high and S is low, while a reset signal is activated when R is low and S is high.
In D-Latch mode, the Q and Q- bar outputs respond to logical changes of the D and clock inputs when the R/S pins are in the high-impedance state. A logical high input is connected to the D pin, then a low logic is applied to the C pin on the device. Depending on the clock signal, the level of high on the D pin is either passed onto the Q or Q- bar output.
In Edge-Triggered D Flip-Flop mode, the device captures the state of the data pin on the activating edge of the clock signal. When the clock signal is low, any change in the data will change the output as soon as the clock signal changes to high. When the clock signal is high, any change in the data will not change the output until the clock signal changes back to low.
The SN74LV573ADBR is the ideal choice for applications that require latching, data storage, temporary data storage, and clocked memory. It is excellent for designing logic circuits, memory circuits, and data buses. In addition, it can be used for circuit isolation and buffering.
The SN74LV573ADBR uses TTL as its logic family. This allows it to operate at 5V and have a fast propagation delay of 7ns. Its logic threshold voltage is 1.5V and its power supply current is 6mA. The device is both static and dynamic, has monolithic silicon gate construction, and is organized into two 8-bit latches. It is a low-power device, operating on 2.7V and consuming a low power of 120μA.
The SN74LV573ADBR is a 5V Dual/Quad device that is categorized as a latch. It can be used for logic circuits and memory circuits, acting as a fast, low-power data storage device. Its TTL logic and 7ns propagation power make it ideal for applications that require rapid data storage. In addition, its monolithic silicon gate construction and 3 different operation modes offer great versatility.
The specific data is subject to PDF, and the above content is for reference
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SN74LV573ADBR Datasheet/PDF