![SN74LVTH16373DGGR Allicdata Electronics](https://files.allicdata.com/upload/common/default.jpg)
SN74LVTH16373DGGR Integrated Circuits (ICs) |
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Allicdata Part #: | 296-8684-2-ND |
Manufacturer Part#: |
SN74LVTH16373DGGR |
Price: | $ 0.00 |
Product Category: | Integrated Circuits (ICs) |
Manufacturer: | Texas Instruments |
Short Description: | IC D-TYPE LATCH TRI-ST 48-TSSOP |
More Detail: | D-Type Transparent Latch 2 Channel 8:8 IC Tri-Stat... |
DataSheet: | ![]() |
Quantity: | 1000 |
Series: | 74LVTH |
Packaging: | Tape & Reel (TR) |
Part Status: | Active |
Logic Type: | D-Type Transparent Latch |
Circuit: | 8:8 |
Output Type: | Tri-State |
Voltage - Supply: | 2.7 V ~ 3.6 V |
Independent Circuits: | 2 |
Delay Time - Propagation: | 3ns |
Current - Output High, Low: | 32mA, 64mA |
Operating Temperature: | -40°C ~ 85°C |
Mounting Type: | Surface Mount |
Package / Case: | 48-TFSOP (0.240", 6.10mm Width) |
Supplier Device Package: | 48-TSSOP |
Base Part Number: | 74LVTH16373 |
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The SN74LVTH16373DGGR falls into the logic family of latches. A latch is a type of circuit that is a combination of logic and memory elements. Depending on its design it can store one bit of information either indefinitely or until reset. Latches are commonly used in logic circuits such as D-type flip flops, and are found in almost all digital logic circuits.
The SN74LVTH16373DGGR is a high speed CMOS 16-bit edge triggered latch with 3-STATE outputs. Its outputs are able to source and sink up to 12 mA each, and can handle a maximum of 5.5 V. It is available in three packages, TSSOP-16, SOIC-16, and VSSOP-16. Clocking can occur with a frequency of up to 50 MHz, and a typical propagation delay of 70 ns.
The SN74LVTH16373DGGR can be used for a variety of applications including bus interfacing, data storage, address matching, and multiplexing. The latch is ideal for applications where reliability and high speed are important. It is well suited for CPLDs and FPGAs where both space and power efficiency are needs.
The SN74LVTH16373DGGR has two basic modes of operation, edge triggered and enabled/disabled. It includes both active-low reset and asynchronous active-low enable inputs. In edge-triggered mode it is triggered by the edge of either the positive or the negative clock pulse, with the data input changing immediately after the clock edge transitions. In enabled/disabled mode the latch is enabled by the active-low enable input (E) and the clock input (C) goes to the output if the enable input is high. It can also be disabled by bringing the C input low.
The SN74LVTH16373DGGR is constructed as two 8-bit edge-triggered latches, with an active-low reset and an active-low enable input. Each latch consists of eight dual-input CMOS gates with an active-low reset input and an active-low enable input. The outputs of the individual logic blocks are connected in series through a set of tri-state drivers to form the 16-bit wide output. The tri-state drivers are controlled by the C input which is active-low disabled when high.
The SN74LVTH16373DGGR is part of the TTL logic family of latches, and thanks to its low-power consumption, high speed, and multiple clocking capabilities, it is ideal for many applications in modern computer systems, communications, industrial control, and robotics.
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