STM32F207VCT6TR

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1. Describe

The STM32F20x series is based on the high-performance Arm® Cortex®-M3 32-bit RISC core with an operating frequency of up to 120 MHz. This series contains high-speed embedded memory (up to 1 MB of flash memory, up to 128 KB of system SRAM), up to Up to 4 KB of backup SRAM, and a wide range of enhanced I/O and peripherals connected to two APB buses, three AHB buses, and a 32-bit multi-AHB bus matrix. These devices also have an adaptive real-time memory accelerator (ART Accelerator™) This allows performance equivalent to executing a 0 wait state program from flash memory at CPU frequencies up to 120 MHz. This performance has been verified using the CoreMark® benchmark. All devices provide three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers, including two PWM timers for motor control and two general-purpose 32-bit timers. Real random generator (RNG). They also have standard and advanced communication interfaces. New advanced peripherals include SDIO, an enhanced flexible static memory control (FSMC) interface (for devices in packages of 100 pins and above), and a camera interface for CMOS sensors. These devices also have standard peripherals.

STM32F205xx and STM32F207xx devices operate at temperatures from –40 to +105 °C Range from 1.8 V to 3.6 V power supply. On WLCSP64+2 encapsulated devices, if IRROFF Set to VDD, when the device is between 0 and Use an external power monitor for the temperature range of 70 °C (see section 3.16). A comprehensive set of energy-saving modes supports the design of low-power applications. STM32F205xx and STM32F207xx devices are available in various packages, from 64 To 176 pins. The included peripheral device group varies with the selected device.

2. Features

    1. Core: Arm® 32-bit Cortex®-M3 CPU (120 MHz max) with Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution performance from Flash memory, MPU, 150 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1)

    2. Memories

        – Up to 1 Mbyte of Flash memory

        – 512 bytes of OTP memory

        – Up to 128 + 4 Kbytes of SRAM

        – Flexible static memory controller that supports Compact Flash, SRAM, PSRAM, NOR and NAND memories

        – LCD parallel interface, 8080/6800 modes

    3. Clock, reset and supply management

        – From 1.8 to 3.6 V application supply + I/Os

        – POR, PDR, PVD and BOR

        – 4 to 26 MHz crystal oscillator

        – Internal 16 MHz factory-trimmed RC

        – 32 kHz oscillator for RTC with calibration

        – Internal 32 kHz RC with calibration

    4. Low-power modes

        – Sleep, Stop and Standby modes

        – VBAT supply for RTC, 20 × 32 bit backup registers, and optional 4 Kbytes backup SRAM

    5. 3 × 12-bit, 0.5 µs ADCs with up to 24 channels and up to 6 MSPS in triple interleaved mode

    6. 2 × 12-bit D/A converters

    7. General-purpose DMA: 16-stream controller with centralized FIFOs and burst support

    8. Up to 17 timers

        – Up to twelve 16-bit and two 32-bit timers, up to 120 MHz, each with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input

    9. Debug mode: Serial wire debug (SWD), JTAG, and Cortex®-M3 Embedded Trace Macrocell™

  10. Up to 140 I/O ports with interrupt capability:

        – Up to 136 fast I/Os up to 60 MHz

        – Up to 138 5 V-tolerant I/Os

  11. Up to 15 communication interfaces

        – Up to three I2C interfaces (SMBus/PMBus)

        – Up to four USARTs and two UARTs (7.5 Mbit/s, ISO 7816 interface, LIN, IrDA, modem control)

        – Up to three SPIs (30 Mbit/s), two with muxed I2S to achieve audio class accuracy via audio PLL or external PLL

        – 2 × CAN interfaces (2.0B Active)

        – SDIO interface

  12. Advanced connectivity

        – USB 2.0 full-speed device/host/OTG controller with on-chip PHY

        – USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI

        – 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII

  13. 8- to 14-bit parallel camera interface (48 Mbyte/s max.)

  14. CRC calculation unit

  15. 96-bit unique ID

3. Pin configuration

4. Pin description